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clk: rockchip: add ability to specify pll-specific flags

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This adds a flag parameter to plls that allows us to create
special flags to tweak the behaviour of the plls if necessary.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Heiko Stuebner
2014-11-20 20:38:50 +01:00
parent 12c0a0e81e
commit 4f8a7c549f
5 changed files with 19 additions and 13 deletions
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3
drivers/clk/rockchip/clk.c
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@@ -199,7 +199,8 @@ void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
list->parent_names, list->num_parents,
reg_base, list->con_offset, grf_lock_offset,
list->lock_shift, list->mode_offset,
list->mode_shift, list->rate_table, &clk_lock);
list->mode_shift, list->rate_table,
list->pll_flags, &clk_lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);