Merge branch 'irqchip/gic-vic-move' into next/virt
Этот коммит содержится в:
Olof Johansson
@@ -1,26 +1,3 @@
|
||||
config ARM_GIC
|
||||
bool
|
||||
select IRQ_DOMAIN
|
||||
select MULTI_IRQ_HANDLER
|
||||
|
||||
config GIC_NON_BANKED
|
||||
bool
|
||||
|
||||
config ARM_VIC
|
||||
bool
|
||||
select IRQ_DOMAIN
|
||||
select MULTI_IRQ_HANDLER
|
||||
|
||||
config ARM_VIC_NR
|
||||
int
|
||||
default 4 if ARCH_S5PV210
|
||||
default 3 if ARCH_S5PC100
|
||||
default 2
|
||||
depends on ARM_VIC
|
||||
help
|
||||
The maximum number of VICs available in the system, for
|
||||
power management.
|
||||
|
||||
config ICST
|
||||
bool
|
||||
|
||||
|
||||
@@ -2,8 +2,6 @@
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARM_GIC) += gic.o
|
||||
obj-$(CONFIG_ARM_VIC) += vic.o
|
||||
obj-$(CONFIG_ICST) += icst.o
|
||||
obj-$(CONFIG_SA1111) += sa1111.o
|
||||
obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
|
||||
|
||||
@@ -1,832 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/common/gic.c
|
||||
*
|
||||
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Interrupt architecture for the GIC:
|
||||
*
|
||||
* o There is one Interrupt Distributor, which receives interrupts
|
||||
* from system devices and sends them to the Interrupt Controllers.
|
||||
*
|
||||
* o There is one CPU Interface per CPU, which sends interrupts sent
|
||||
* by the Distributor, and interrupts generated locally, to the
|
||||
* associated CPU. The base address of the CPU interface is usually
|
||||
* aliased so that the same address points to different chips depending
|
||||
* on the CPU it is accessed from.
|
||||
*
|
||||
* Note that IRQs 0-31 are special - they are local to each CPU.
|
||||
* As such, the enable set/clear, pending set/clear and active bit
|
||||
* registers are banked per-cpu for these sources.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
union gic_base {
|
||||
void __iomem *common_base;
|
||||
void __percpu __iomem **percpu_base;
|
||||
};
|
||||
|
||||
struct gic_chip_data {
|
||||
union gic_base dist_base;
|
||||
union gic_base cpu_base;
|
||||
#ifdef CONFIG_CPU_PM
|
||||
u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
|
||||
u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
|
||||
u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
|
||||
u32 __percpu *saved_ppi_enable;
|
||||
u32 __percpu *saved_ppi_conf;
|
||||
#endif
|
||||
struct irq_domain *domain;
|
||||
unsigned int gic_irqs;
|
||||
#ifdef CONFIG_GIC_NON_BANKED
|
||||
void __iomem *(*get_base)(union gic_base *);
|
||||
#endif
|
||||
};
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
|
||||
|
||||
/*
|
||||
* The GIC mapping of CPU interfaces does not necessarily match
|
||||
* the logical CPU numbering. Let's use a mapping as returned
|
||||
* by the GIC itself.
|
||||
*/
|
||||
#define NR_GIC_CPU_IF 8
|
||||
static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
|
||||
|
||||
/*
|
||||
* Supported arch specific GIC irq extension.
|
||||
* Default make them NULL.
|
||||
*/
|
||||
struct irq_chip gic_arch_extn = {
|
||||
.irq_eoi = NULL,
|
||||
.irq_mask = NULL,
|
||||
.irq_unmask = NULL,
|
||||
.irq_retrigger = NULL,
|
||||
.irq_set_type = NULL,
|
||||
.irq_set_wake = NULL,
|
||||
};
|
||||
|
||||
#ifndef MAX_GIC_NR
|
||||
#define MAX_GIC_NR 1
|
||||
#endif
|
||||
|
||||
static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
|
||||
|
||||
#ifdef CONFIG_GIC_NON_BANKED
|
||||
static void __iomem *gic_get_percpu_base(union gic_base *base)
|
||||
{
|
||||
return *__this_cpu_ptr(base->percpu_base);
|
||||
}
|
||||
|
||||
static void __iomem *gic_get_common_base(union gic_base *base)
|
||||
{
|
||||
return base->common_base;
|
||||
}
|
||||
|
||||
static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
|
||||
{
|
||||
return data->get_base(&data->dist_base);
|
||||
}
|
||||
|
||||
static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
|
||||
{
|
||||
return data->get_base(&data->cpu_base);
|
||||
}
|
||||
|
||||
static inline void gic_set_base_accessor(struct gic_chip_data *data,
|
||||
void __iomem *(*f)(union gic_base *))
|
||||
{
|
||||
data->get_base = f;
|
||||
}
|
||||
#else
|
||||
#define gic_data_dist_base(d) ((d)->dist_base.common_base)
|
||||
#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
|
||||
#define gic_set_base_accessor(d,f)
|
||||
#endif
|
||||
|
||||
static inline void __iomem *gic_dist_base(struct irq_data *d)
|
||||
{
|
||||
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
|
||||
return gic_data_dist_base(gic_data);
|
||||
}
|
||||
|
||||
static inline void __iomem *gic_cpu_base(struct irq_data *d)
|
||||
{
|
||||
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
|
||||
return gic_data_cpu_base(gic_data);
|
||||
}
|
||||
|
||||
static inline unsigned int gic_irq(struct irq_data *d)
|
||||
{
|
||||
return d->hwirq;
|
||||
}
|
||||
|
||||
/*
|
||||
* Routines to acknowledge, disable and enable interrupts
|
||||
*/
|
||||
static void gic_mask_irq(struct irq_data *d)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
|
||||
if (gic_arch_extn.irq_mask)
|
||||
gic_arch_extn.irq_mask(d);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
}
|
||||
|
||||
static void gic_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
if (gic_arch_extn.irq_unmask)
|
||||
gic_arch_extn.irq_unmask(d);
|
||||
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
}
|
||||
|
||||
static void gic_eoi_irq(struct irq_data *d)
|
||||
{
|
||||
if (gic_arch_extn.irq_eoi) {
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
gic_arch_extn.irq_eoi(d);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
}
|
||||
|
||||
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
|
||||
}
|
||||
|
||||
static int gic_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
void __iomem *base = gic_dist_base(d);
|
||||
unsigned int gicirq = gic_irq(d);
|
||||
u32 enablemask = 1 << (gicirq % 32);
|
||||
u32 enableoff = (gicirq / 32) * 4;
|
||||
u32 confmask = 0x2 << ((gicirq % 16) * 2);
|
||||
u32 confoff = (gicirq / 16) * 4;
|
||||
bool enabled = false;
|
||||
u32 val;
|
||||
|
||||
/* Interrupt configuration for SGIs can't be changed */
|
||||
if (gicirq < 16)
|
||||
return -EINVAL;
|
||||
|
||||
if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
|
||||
if (gic_arch_extn.irq_set_type)
|
||||
gic_arch_extn.irq_set_type(d, type);
|
||||
|
||||
val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
|
||||
if (type == IRQ_TYPE_LEVEL_HIGH)
|
||||
val &= ~confmask;
|
||||
else if (type == IRQ_TYPE_EDGE_RISING)
|
||||
val |= confmask;
|
||||
|
||||
/*
|
||||
* As recommended by the spec, disable the interrupt before changing
|
||||
* the configuration
|
||||
*/
|
||||
if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
|
||||
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
|
||||
enabled = true;
|
||||
}
|
||||
|
||||
writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
|
||||
|
||||
if (enabled)
|
||||
writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
|
||||
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gic_retrigger(struct irq_data *d)
|
||||
{
|
||||
if (gic_arch_extn.irq_retrigger)
|
||||
return gic_arch_extn.irq_retrigger(d);
|
||||
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
||||
bool force)
|
||||
{
|
||||
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
|
||||
unsigned int shift = (gic_irq(d) % 4) * 8;
|
||||
unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
||||
u32 val, mask, bit;
|
||||
|
||||
if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
|
||||
return -EINVAL;
|
||||
|
||||
mask = 0xff << shift;
|
||||
bit = gic_cpu_map[cpu] << shift;
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
val = readl_relaxed(reg) & ~mask;
|
||||
writel_relaxed(val | bit, reg);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
|
||||
return IRQ_SET_MASK_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int gic_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
int ret = -ENXIO;
|
||||
|
||||
if (gic_arch_extn.irq_set_wake)
|
||||
ret = gic_arch_extn.irq_set_wake(d, on);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#else
|
||||
#define gic_set_wake NULL
|
||||
#endif
|
||||
|
||||
asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
u32 irqstat, irqnr;
|
||||
struct gic_chip_data *gic = &gic_data[0];
|
||||
void __iomem *cpu_base = gic_data_cpu_base(gic);
|
||||
|
||||
do {
|
||||
irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
|
||||
irqnr = irqstat & ~0x1c00;
|
||||
|
||||
if (likely(irqnr > 15 && irqnr < 1021)) {
|
||||
irqnr = irq_find_mapping(gic->domain, irqnr);
|
||||
handle_IRQ(irqnr, regs);
|
||||
continue;
|
||||
}
|
||||
if (irqnr < 16) {
|
||||
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
|
||||
#ifdef CONFIG_SMP
|
||||
handle_IPI(irqnr, regs);
|
||||
#endif
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
unsigned int cascade_irq, gic_irq;
|
||||
unsigned long status;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
|
||||
gic_irq = (status & 0x3ff);
|
||||
if (gic_irq == 1023)
|
||||
goto out;
|
||||
|
||||
cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
|
||||
if (unlikely(gic_irq < 32 || gic_irq > 1020))
|
||||
do_bad_IRQ(cascade_irq, desc);
|
||||
else
|
||||
generic_handle_irq(cascade_irq);
|
||||
|
||||
out:
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static struct irq_chip gic_chip = {
|
||||
.name = "GIC",
|
||||
.irq_mask = gic_mask_irq,
|
||||
.irq_unmask = gic_unmask_irq,
|
||||
.irq_eoi = gic_eoi_irq,
|
||||
.irq_set_type = gic_set_type,
|
||||
.irq_retrigger = gic_retrigger,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = gic_set_affinity,
|
||||
#endif
|
||||
.irq_set_wake = gic_set_wake,
|
||||
};
|
||||
|
||||
void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
|
||||
{
|
||||
if (gic_nr >= MAX_GIC_NR)
|
||||
BUG();
|
||||
if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
|
||||
BUG();
|
||||
irq_set_chained_handler(irq, gic_handle_cascade_irq);
|
||||
}
|
||||
|
||||
static u8 gic_get_cpumask(struct gic_chip_data *gic)
|
||||
{
|
||||
void __iomem *base = gic_data_dist_base(gic);
|
||||
u32 mask, i;
|
||||
|
||||
for (i = mask = 0; i < 32; i += 4) {
|
||||
mask = readl_relaxed(base + GIC_DIST_TARGET + i);
|
||||
mask |= mask >> 16;
|
||||
mask |= mask >> 8;
|
||||
if (mask)
|
||||
break;
|
||||
}
|
||||
|
||||
if (!mask)
|
||||
pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
static void __init gic_dist_init(struct gic_chip_data *gic)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 cpumask;
|
||||
unsigned int gic_irqs = gic->gic_irqs;
|
||||
void __iomem *base = gic_data_dist_base(gic);
|
||||
|
||||
writel_relaxed(0, base + GIC_DIST_CTRL);
|
||||
|
||||
/*
|
||||
* Set all global interrupts to be level triggered, active low.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 16)
|
||||
writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
|
||||
|
||||
/*
|
||||
* Set all global interrupts to this CPU only.
|
||||
*/
|
||||
cpumask = gic_get_cpumask(gic);
|
||||
cpumask |= cpumask << 8;
|
||||
cpumask |= cpumask << 16;
|
||||
for (i = 32; i < gic_irqs; i += 4)
|
||||
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
|
||||
|
||||
/*
|
||||
* Set priority on all global interrupts.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 4)
|
||||
writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
|
||||
|
||||
/*
|
||||
* Disable all interrupts. Leave the PPI and SGIs alone
|
||||
* as these enables are banked registers.
|
||||
*/
|
||||
for (i = 32; i < gic_irqs; i += 32)
|
||||
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
|
||||
|
||||
writel_relaxed(1, base + GIC_DIST_CTRL);
|
||||
}
|
||||
|
||||
static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
|
||||
{
|
||||
void __iomem *dist_base = gic_data_dist_base(gic);
|
||||
void __iomem *base = gic_data_cpu_base(gic);
|
||||
unsigned int cpu_mask, cpu = smp_processor_id();
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Get what the GIC says our CPU mask is.
|
||||
*/
|
||||
BUG_ON(cpu >= NR_GIC_CPU_IF);
|
||||
cpu_mask = gic_get_cpumask(gic);
|
||||
gic_cpu_map[cpu] = cpu_mask;
|
||||
|
||||
/*
|
||||
* Clear our mask from the other map entries in case they're
|
||||
* still undefined.
|
||||
*/
|
||||
for (i = 0; i < NR_GIC_CPU_IF; i++)
|
||||
if (i != cpu)
|
||||
gic_cpu_map[i] &= ~cpu_mask;
|
||||
|
||||
/*
|
||||
* Deal with the banked PPI and SGI interrupts - disable all
|
||||
* PPI interrupts, ensure all SGI interrupts are enabled.
|
||||
*/
|
||||
writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
|
||||
writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
|
||||
|
||||
/*
|
||||
* Set priority on PPI and SGI interrupts
|
||||
*/
|
||||
for (i = 0; i < 32; i += 4)
|
||||
writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
|
||||
|
||||
writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
|
||||
writel_relaxed(1, base + GIC_CPU_CTRL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_PM
|
||||
/*
|
||||
* Saves the GIC distributor registers during suspend or idle. Must be called
|
||||
* with interrupts disabled but before powering down the GIC. After calling
|
||||
* this function, no interrupts will be delivered by the GIC, and another
|
||||
* platform-specific wakeup source must be enabled.
|
||||
*/
|
||||
static void gic_dist_save(unsigned int gic_nr)
|
||||
{
|
||||
unsigned int gic_irqs;
|
||||
void __iomem *dist_base;
|
||||
int i;
|
||||
|
||||
if (gic_nr >= MAX_GIC_NR)
|
||||
BUG();
|
||||
|
||||
gic_irqs = gic_data[gic_nr].gic_irqs;
|
||||
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
||||
|
||||
if (!dist_base)
|
||||
return;
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
|
||||
gic_data[gic_nr].saved_spi_conf[i] =
|
||||
readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
||||
gic_data[gic_nr].saved_spi_target[i] =
|
||||
readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
|
||||
gic_data[gic_nr].saved_spi_enable[i] =
|
||||
readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* Restores the GIC distributor registers during resume or when coming out of
|
||||
* idle. Must be called before enabling interrupts. If a level interrupt
|
||||
* that occured while the GIC was suspended is still present, it will be
|
||||
* handled normally, but any edge interrupts that occured will not be seen by
|
||||
* the GIC and need to be handled by the platform-specific wakeup source.
|
||||
*/
|
||||
static void gic_dist_restore(unsigned int gic_nr)
|
||||
{
|
||||
unsigned int gic_irqs;
|
||||
unsigned int i;
|
||||
void __iomem *dist_base;
|
||||
|
||||
if (gic_nr >= MAX_GIC_NR)
|
||||
BUG();
|
||||
|
||||
gic_irqs = gic_data[gic_nr].gic_irqs;
|
||||
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
||||
|
||||
if (!dist_base)
|
||||
return;
|
||||
|
||||
writel_relaxed(0, dist_base + GIC_DIST_CTRL);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
|
||||
writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
|
||||
dist_base + GIC_DIST_CONFIG + i * 4);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
||||
writel_relaxed(0xa0a0a0a0,
|
||||
dist_base + GIC_DIST_PRI + i * 4);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
||||
writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
|
||||
dist_base + GIC_DIST_TARGET + i * 4);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
|
||||
writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
|
||||
dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
||||
|
||||
writel_relaxed(1, dist_base + GIC_DIST_CTRL);
|
||||
}
|
||||
|
||||
static void gic_cpu_save(unsigned int gic_nr)
|
||||
{
|
||||
int i;
|
||||
u32 *ptr;
|
||||
void __iomem *dist_base;
|
||||
void __iomem *cpu_base;
|
||||
|
||||
if (gic_nr >= MAX_GIC_NR)
|
||||
BUG();
|
||||
|
||||
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
||||
cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
|
||||
|
||||
if (!dist_base || !cpu_base)
|
||||
return;
|
||||
|
||||
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
|
||||
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
|
||||
ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
||||
|
||||
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
|
||||
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
|
||||
ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
|
||||
|
||||
}
|
||||
|
||||
static void gic_cpu_restore(unsigned int gic_nr)
|
||||
{
|
||||
int i;
|
||||
u32 *ptr;
|
||||
void __iomem *dist_base;
|
||||
void __iomem *cpu_base;
|
||||
|
||||
if (gic_nr >= MAX_GIC_NR)
|
||||
BUG();
|
||||
|
||||
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
||||
cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
|
||||
|
||||
if (!dist_base || !cpu_base)
|
||||
return;
|
||||
|
||||
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
|
||||
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
|
||||
writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
||||
|
||||
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
|
||||
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
|
||||
writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
|
||||
writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
|
||||
|
||||
writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
|
||||
writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
|
||||
}
|
||||
|
||||
static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_GIC_NR; i++) {
|
||||
#ifdef CONFIG_GIC_NON_BANKED
|
||||
/* Skip over unused GICs */
|
||||
if (!gic_data[i].get_base)
|
||||
continue;
|
||||
#endif
|
||||
switch (cmd) {
|
||||
case CPU_PM_ENTER:
|
||||
gic_cpu_save(i);
|
||||
break;
|
||||
case CPU_PM_ENTER_FAILED:
|
||||
case CPU_PM_EXIT:
|
||||
gic_cpu_restore(i);
|
||||
break;
|
||||
case CPU_CLUSTER_PM_ENTER:
|
||||
gic_dist_save(i);
|
||||
break;
|
||||
case CPU_CLUSTER_PM_ENTER_FAILED:
|
||||
case CPU_CLUSTER_PM_EXIT:
|
||||
gic_dist_restore(i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block gic_notifier_block = {
|
||||
.notifier_call = gic_notifier,
|
||||
};
|
||||
|
||||
static void __init gic_pm_init(struct gic_chip_data *gic)
|
||||
{
|
||||
gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
|
||||
sizeof(u32));
|
||||
BUG_ON(!gic->saved_ppi_enable);
|
||||
|
||||
gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
|
||||
sizeof(u32));
|
||||
BUG_ON(!gic->saved_ppi_conf);
|
||||
|
||||
if (gic == &gic_data[0])
|
||||
cpu_pm_register_notifier(&gic_notifier_block);
|
||||
}
|
||||
#else
|
||||
static void __init gic_pm_init(struct gic_chip_data *gic)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
if (hw < 32) {
|
||||
irq_set_percpu_devid(irq);
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_percpu_devid_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
||||
} else {
|
||||
irq_set_chip_and_handler(irq, &gic_chip,
|
||||
handle_fasteoi_irq);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
irq_set_chip_data(irq, d->host_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gic_irq_domain_xlate(struct irq_domain *d,
|
||||
struct device_node *controller,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
unsigned long *out_hwirq, unsigned int *out_type)
|
||||
{
|
||||
if (d->of_node != controller)
|
||||
return -EINVAL;
|
||||
if (intsize < 3)
|
||||
return -EINVAL;
|
||||
|
||||
/* Get the interrupt number and add 16 to skip over SGIs */
|
||||
*out_hwirq = intspec[1] + 16;
|
||||
|
||||
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
|
||||
if (!intspec[0])
|
||||
*out_hwirq += 16;
|
||||
|
||||
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct irq_domain_ops gic_irq_domain_ops = {
|
||||
.map = gic_irq_domain_map,
|
||||
.xlate = gic_irq_domain_xlate,
|
||||
};
|
||||
|
||||
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
||||
void __iomem *dist_base, void __iomem *cpu_base,
|
||||
u32 percpu_offset, struct device_node *node)
|
||||
{
|
||||
irq_hw_number_t hwirq_base;
|
||||
struct gic_chip_data *gic;
|
||||
int gic_irqs, irq_base, i;
|
||||
|
||||
BUG_ON(gic_nr >= MAX_GIC_NR);
|
||||
|
||||
gic = &gic_data[gic_nr];
|
||||
#ifdef CONFIG_GIC_NON_BANKED
|
||||
if (percpu_offset) { /* Frankein-GIC without banked registers... */
|
||||
unsigned int cpu;
|
||||
|
||||
gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
|
||||
gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
|
||||
if (WARN_ON(!gic->dist_base.percpu_base ||
|
||||
!gic->cpu_base.percpu_base)) {
|
||||
free_percpu(gic->dist_base.percpu_base);
|
||||
free_percpu(gic->cpu_base.percpu_base);
|
||||
return;
|
||||
}
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
unsigned long offset = percpu_offset * cpu_logical_map(cpu);
|
||||
*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
|
||||
*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
|
||||
}
|
||||
|
||||
gic_set_base_accessor(gic, gic_get_percpu_base);
|
||||
} else
|
||||
#endif
|
||||
{ /* Normal, sane GIC... */
|
||||
WARN(percpu_offset,
|
||||
"GIC_NON_BANKED not enabled, ignoring %08x offset!",
|
||||
percpu_offset);
|
||||
gic->dist_base.common_base = dist_base;
|
||||
gic->cpu_base.common_base = cpu_base;
|
||||
gic_set_base_accessor(gic, gic_get_common_base);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the CPU interface map to all CPUs.
|
||||
* It will be refined as each CPU probes its ID.
|
||||
*/
|
||||
for (i = 0; i < NR_GIC_CPU_IF; i++)
|
||||
gic_cpu_map[i] = 0xff;
|
||||
|
||||
/*
|
||||
* For primary GICs, skip over SGIs.
|
||||
* For secondary GICs, skip over PPIs, too.
|
||||
*/
|
||||
if (gic_nr == 0 && (irq_start & 31) > 0) {
|
||||
hwirq_base = 16;
|
||||
if (irq_start != -1)
|
||||
irq_start = (irq_start & ~31) + 16;
|
||||
} else {
|
||||
hwirq_base = 32;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find out how many interrupts are supported.
|
||||
* The GIC only supports up to 1020 interrupt sources.
|
||||
*/
|
||||
gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
|
||||
gic_irqs = (gic_irqs + 1) * 32;
|
||||
if (gic_irqs > 1020)
|
||||
gic_irqs = 1020;
|
||||
gic->gic_irqs = gic_irqs;
|
||||
|
||||
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
|
||||
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
|
||||
if (IS_ERR_VALUE(irq_base)) {
|
||||
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
|
||||
irq_start);
|
||||
irq_base = irq_start;
|
||||
}
|
||||
gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
|
||||
hwirq_base, &gic_irq_domain_ops, gic);
|
||||
if (WARN_ON(!gic->domain))
|
||||
return;
|
||||
|
||||
gic_chip.flags |= gic_arch_extn.flags;
|
||||
gic_dist_init(gic);
|
||||
gic_cpu_init(gic);
|
||||
gic_pm_init(gic);
|
||||
}
|
||||
|
||||
void __cpuinit gic_secondary_init(unsigned int gic_nr)
|
||||
{
|
||||
BUG_ON(gic_nr >= MAX_GIC_NR);
|
||||
|
||||
gic_cpu_init(&gic_data[gic_nr]);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
|
||||
{
|
||||
int cpu;
|
||||
unsigned long map = 0;
|
||||
|
||||
/* Convert our logical CPU mask into a physical one. */
|
||||
for_each_cpu(cpu, mask)
|
||||
map |= gic_cpu_map[cpu];
|
||||
|
||||
/*
|
||||
* Ensure that stores to Normal memory are visible to the
|
||||
* other CPUs before issuing the IPI.
|
||||
*/
|
||||
dsb();
|
||||
|
||||
/* this always happens on GIC0 */
|
||||
writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static int gic_cnt __initdata = 0;
|
||||
|
||||
int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
void __iomem *cpu_base;
|
||||
void __iomem *dist_base;
|
||||
u32 percpu_offset;
|
||||
int irq;
|
||||
|
||||
if (WARN_ON(!node))
|
||||
return -ENODEV;
|
||||
|
||||
dist_base = of_iomap(node, 0);
|
||||
WARN(!dist_base, "unable to map gic dist registers\n");
|
||||
|
||||
cpu_base = of_iomap(node, 1);
|
||||
WARN(!cpu_base, "unable to map gic cpu registers\n");
|
||||
|
||||
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
|
||||
percpu_offset = 0;
|
||||
|
||||
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
|
||||
|
||||
if (parent) {
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
gic_cascade_irq(gic_cnt, irq);
|
||||
}
|
||||
gic_cnt++;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -1,464 +0,0 @@
|
||||
/*
|
||||
* linux/arch/arm/common/vic.c
|
||||
*
|
||||
* Copyright (C) 1999 - 2003 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
#include <asm/exception.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
/**
|
||||
* struct vic_device - VIC PM device
|
||||
* @irq: The IRQ number for the base of the VIC.
|
||||
* @base: The register base for the VIC.
|
||||
* @valid_sources: A bitmask of valid interrupts
|
||||
* @resume_sources: A bitmask of interrupts for resume.
|
||||
* @resume_irqs: The IRQs enabled for resume.
|
||||
* @int_select: Save for VIC_INT_SELECT.
|
||||
* @int_enable: Save for VIC_INT_ENABLE.
|
||||
* @soft_int: Save for VIC_INT_SOFT.
|
||||
* @protect: Save for VIC_PROTECT.
|
||||
* @domain: The IRQ domain for the VIC.
|
||||
*/
|
||||
struct vic_device {
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
u32 valid_sources;
|
||||
u32 resume_sources;
|
||||
u32 resume_irqs;
|
||||
u32 int_select;
|
||||
u32 int_enable;
|
||||
u32 soft_int;
|
||||
u32 protect;
|
||||
struct irq_domain *domain;
|
||||
};
|
||||
|
||||
/* we cannot allocate memory when VICs are initially registered */
|
||||
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
|
||||
|
||||
static int vic_id;
|
||||
|
||||
/**
|
||||
* vic_init2 - common initialisation code
|
||||
* @base: Base of the VIC.
|
||||
*
|
||||
* Common initialisation code for registration
|
||||
* and resume.
|
||||
*/
|
||||
static void vic_init2(void __iomem *base)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
|
||||
writel(VIC_VECT_CNTL_ENABLE | i, reg);
|
||||
}
|
||||
|
||||
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static void resume_one_vic(struct vic_device *vic)
|
||||
{
|
||||
void __iomem *base = vic->base;
|
||||
|
||||
printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
|
||||
|
||||
/* re-initialise static settings */
|
||||
vic_init2(base);
|
||||
|
||||
writel(vic->int_select, base + VIC_INT_SELECT);
|
||||
writel(vic->protect, base + VIC_PROTECT);
|
||||
|
||||
/* set the enabled ints and then clear the non-enabled */
|
||||
writel(vic->int_enable, base + VIC_INT_ENABLE);
|
||||
writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
|
||||
|
||||
/* and the same for the soft-int register */
|
||||
|
||||
writel(vic->soft_int, base + VIC_INT_SOFT);
|
||||
writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_resume(void)
|
||||
{
|
||||
int id;
|
||||
|
||||
for (id = vic_id - 1; id >= 0; id--)
|
||||
resume_one_vic(vic_devices + id);
|
||||
}
|
||||
|
||||
static void suspend_one_vic(struct vic_device *vic)
|
||||
{
|
||||
void __iomem *base = vic->base;
|
||||
|
||||
printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
|
||||
|
||||
vic->int_select = readl(base + VIC_INT_SELECT);
|
||||
vic->int_enable = readl(base + VIC_INT_ENABLE);
|
||||
vic->soft_int = readl(base + VIC_INT_SOFT);
|
||||
vic->protect = readl(base + VIC_PROTECT);
|
||||
|
||||
/* set the interrupts (if any) that are used for
|
||||
* resuming the system */
|
||||
|
||||
writel(vic->resume_irqs, base + VIC_INT_ENABLE);
|
||||
writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
|
||||
}
|
||||
|
||||
static int vic_suspend(void)
|
||||
{
|
||||
int id;
|
||||
|
||||
for (id = 0; id < vic_id; id++)
|
||||
suspend_one_vic(vic_devices + id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct syscore_ops vic_syscore_ops = {
|
||||
.suspend = vic_suspend,
|
||||
.resume = vic_resume,
|
||||
};
|
||||
|
||||
/**
|
||||
* vic_pm_init - initicall to register VIC pm
|
||||
*
|
||||
* This is called via late_initcall() to register
|
||||
* the resources for the VICs due to the early
|
||||
* nature of the VIC's registration.
|
||||
*/
|
||||
static int __init vic_pm_init(void)
|
||||
{
|
||||
if (vic_id > 0)
|
||||
register_syscore_ops(&vic_syscore_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
late_initcall(vic_pm_init);
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static struct irq_chip vic_chip;
|
||||
|
||||
static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
struct vic_device *v = d->host_data;
|
||||
|
||||
/* Skip invalid IRQs, only register handlers for the real ones */
|
||||
if (!(v->valid_sources & (1 << hwirq)))
|
||||
return -ENOTSUPP;
|
||||
irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
|
||||
irq_set_chip_data(irq, v->base);
|
||||
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops vic_irqdomain_ops = {
|
||||
.map = vic_irqdomain_map,
|
||||
.xlate = irq_domain_xlate_onetwocell,
|
||||
};
|
||||
|
||||
/**
|
||||
* vic_register() - Register a VIC.
|
||||
* @base: The base address of the VIC.
|
||||
* @irq: The base IRQ for the VIC.
|
||||
* @valid_sources: bitmask of valid interrupts
|
||||
* @resume_sources: bitmask of interrupts allowed for resume sources.
|
||||
* @node: The device tree node associated with the VIC.
|
||||
*
|
||||
* Register the VIC with the system device tree so that it can be notified
|
||||
* of suspend and resume requests and ensure that the correct actions are
|
||||
* taken to re-instate the settings on resume.
|
||||
*
|
||||
* This also configures the IRQ domain for the VIC.
|
||||
*/
|
||||
static void __init vic_register(void __iomem *base, unsigned int irq,
|
||||
u32 valid_sources, u32 resume_sources,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct vic_device *v;
|
||||
int i;
|
||||
|
||||
if (vic_id >= ARRAY_SIZE(vic_devices)) {
|
||||
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
v = &vic_devices[vic_id];
|
||||
v->base = base;
|
||||
v->valid_sources = valid_sources;
|
||||
v->resume_sources = resume_sources;
|
||||
v->irq = irq;
|
||||
vic_id++;
|
||||
v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
|
||||
&vic_irqdomain_ops, v);
|
||||
/* create an IRQ mapping for each valid IRQ */
|
||||
for (i = 0; i < fls(valid_sources); i++)
|
||||
if (valid_sources & (1 << i))
|
||||
irq_create_mapping(v->domain, i);
|
||||
}
|
||||
|
||||
static void vic_ack_irq(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
unsigned int irq = d->hwirq;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
|
||||
/* moreover, clear the soft-triggered, in case it was the reason */
|
||||
writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_mask_irq(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
unsigned int irq = d->hwirq;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
|
||||
}
|
||||
|
||||
static void vic_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = irq_data_get_irq_chip_data(d);
|
||||
unsigned int irq = d->hwirq;
|
||||
writel(1 << irq, base + VIC_INT_ENABLE);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM)
|
||||
static struct vic_device *vic_from_irq(unsigned int irq)
|
||||
{
|
||||
struct vic_device *v = vic_devices;
|
||||
unsigned int base_irq = irq & ~31;
|
||||
int id;
|
||||
|
||||
for (id = 0; id < vic_id; id++, v++) {
|
||||
if (v->irq == base_irq)
|
||||
return v;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int vic_set_wake(struct irq_data *d, unsigned int on)
|
||||
{
|
||||
struct vic_device *v = vic_from_irq(d->irq);
|
||||
unsigned int off = d->hwirq;
|
||||
u32 bit = 1 << off;
|
||||
|
||||
if (!v)
|
||||
return -EINVAL;
|
||||
|
||||
if (!(bit & v->resume_sources))
|
||||
return -EINVAL;
|
||||
|
||||
if (on)
|
||||
v->resume_irqs |= bit;
|
||||
else
|
||||
v->resume_irqs &= ~bit;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define vic_set_wake NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static struct irq_chip vic_chip = {
|
||||
.name = "VIC",
|
||||
.irq_ack = vic_ack_irq,
|
||||
.irq_mask = vic_mask_irq,
|
||||
.irq_unmask = vic_unmask_irq,
|
||||
.irq_set_wake = vic_set_wake,
|
||||
};
|
||||
|
||||
static void __init vic_disable(void __iomem *base)
|
||||
{
|
||||
writel(0, base + VIC_INT_SELECT);
|
||||
writel(0, base + VIC_INT_ENABLE);
|
||||
writel(~0, base + VIC_INT_ENABLE_CLEAR);
|
||||
writel(0, base + VIC_ITCR);
|
||||
writel(~0, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
||||
static void __init vic_clear_interrupts(void __iomem *base)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
writel(0, base + VIC_PL190_VECT_ADDR);
|
||||
for (i = 0; i < 19; i++) {
|
||||
unsigned int value;
|
||||
|
||||
value = readl(base + VIC_PL190_VECT_ADDR);
|
||||
writel(value, base + VIC_PL190_VECT_ADDR);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
|
||||
* The original cell has 32 interrupts, while the modified one has 64,
|
||||
* replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
|
||||
* the probe function is called twice, with base set to offset 000
|
||||
* and 020 within the page. We call this "second block".
|
||||
*/
|
||||
static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources, struct device_node *node)
|
||||
{
|
||||
unsigned int i;
|
||||
int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
|
||||
|
||||
/* Disable all interrupts initially. */
|
||||
vic_disable(base);
|
||||
|
||||
/*
|
||||
* Make sure we clear all existing interrupts. The vector registers
|
||||
* in this cell are after the second block of general registers,
|
||||
* so we can address them using standard offsets, but only from
|
||||
* the second base address, which is 0x20 in the page
|
||||
*/
|
||||
if (vic_2nd_block) {
|
||||
vic_clear_interrupts(base);
|
||||
|
||||
/* ST has 16 vectors as well, but we don't enable them by now */
|
||||
for (i = 0; i < 16; i++) {
|
||||
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
|
||||
writel(0, reg);
|
||||
}
|
||||
|
||||
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
|
||||
}
|
||||
|
||||
vic_register(base, irq_start, vic_sources, 0, node);
|
||||
}
|
||||
|
||||
void __init __vic_init(void __iomem *base, int irq_start,
|
||||
u32 vic_sources, u32 resume_sources,
|
||||
struct device_node *node)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 cellid = 0;
|
||||
enum amba_vendor vendor;
|
||||
|
||||
/* Identify which VIC cell this one is, by reading the ID */
|
||||
for (i = 0; i < 4; i++) {
|
||||
void __iomem *addr;
|
||||
addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
|
||||
cellid |= (readl(addr) & 0xff) << (8 * i);
|
||||
}
|
||||
vendor = (cellid >> 12) & 0xff;
|
||||
printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
|
||||
base, cellid, vendor);
|
||||
|
||||
switch(vendor) {
|
||||
case AMBA_VENDOR_ST:
|
||||
vic_init_st(base, irq_start, vic_sources, node);
|
||||
return;
|
||||
default:
|
||||
printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
|
||||
/* fall through */
|
||||
case AMBA_VENDOR_ARM:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable all interrupts initially. */
|
||||
vic_disable(base);
|
||||
|
||||
/* Make sure we clear all existing interrupts */
|
||||
vic_clear_interrupts(base);
|
||||
|
||||
vic_init2(base);
|
||||
|
||||
vic_register(base, irq_start, vic_sources, resume_sources, node);
|
||||
}
|
||||
|
||||
/**
|
||||
* vic_init() - initialise a vectored interrupt controller
|
||||
* @base: iomem base address
|
||||
* @irq_start: starting interrupt number, must be muliple of 32
|
||||
* @vic_sources: bitmask of interrupt sources to allow
|
||||
* @resume_sources: bitmask of interrupt sources to allow for resume
|
||||
*/
|
||||
void __init vic_init(void __iomem *base, unsigned int irq_start,
|
||||
u32 vic_sources, u32 resume_sources)
|
||||
{
|
||||
__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
int __init vic_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
void __iomem *regs;
|
||||
|
||||
if (WARN(parent, "non-root VICs are not supported"))
|
||||
return -EINVAL;
|
||||
|
||||
regs = of_iomap(node, 0);
|
||||
if (WARN_ON(!regs))
|
||||
return -EIO;
|
||||
|
||||
/*
|
||||
* Passing 0 as first IRQ makes the simple domain allocate descriptors
|
||||
*/
|
||||
__vic_init(regs, 0, ~0, ~0, node);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG OF */
|
||||
|
||||
/*
|
||||
* Handle each interrupt in a single VIC. Returns non-zero if we've
|
||||
* handled at least one interrupt. This reads the status register
|
||||
* before handling each interrupt, which is necessary given that
|
||||
* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
|
||||
*/
|
||||
static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
|
||||
{
|
||||
u32 stat, irq;
|
||||
int handled = 0;
|
||||
|
||||
while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
|
||||
irq = ffs(stat) - 1;
|
||||
handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
return handled;
|
||||
}
|
||||
|
||||
/*
|
||||
* Keep iterating over all registered VIC's until there are no pending
|
||||
* interrupts.
|
||||
*/
|
||||
asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
int i, handled;
|
||||
|
||||
do {
|
||||
for (i = 0, handled = 0; i < vic_id; ++i)
|
||||
handled |= handle_one_vic(&vic_devices[i], regs);
|
||||
} while (handled);
|
||||
}
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* arch/arm/include/asm/hardware/gic.h
|
||||
*
|
||||
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __ASM_ARM_HARDWARE_GIC_H
|
||||
#define __ASM_ARM_HARDWARE_GIC_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#define GIC_CPU_CTRL 0x00
|
||||
#define GIC_CPU_PRIMASK 0x04
|
||||
#define GIC_CPU_BINPOINT 0x08
|
||||
#define GIC_CPU_INTACK 0x0c
|
||||
#define GIC_CPU_EOI 0x10
|
||||
#define GIC_CPU_RUNNINGPRI 0x14
|
||||
#define GIC_CPU_HIGHPRI 0x18
|
||||
|
||||
#define GIC_DIST_CTRL 0x000
|
||||
#define GIC_DIST_CTR 0x004
|
||||
#define GIC_DIST_ENABLE_SET 0x100
|
||||
#define GIC_DIST_ENABLE_CLEAR 0x180
|
||||
#define GIC_DIST_PENDING_SET 0x200
|
||||
#define GIC_DIST_PENDING_CLEAR 0x280
|
||||
#define GIC_DIST_ACTIVE_BIT 0x300
|
||||
#define GIC_DIST_PRI 0x400
|
||||
#define GIC_DIST_TARGET 0x800
|
||||
#define GIC_DIST_CONFIG 0xc00
|
||||
#define GIC_DIST_SOFTINT 0xf00
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/irqdomain.h>
|
||||
struct device_node;
|
||||
|
||||
extern struct irq_chip gic_arch_extn;
|
||||
|
||||
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
|
||||
u32 offset, struct device_node *);
|
||||
int gic_of_init(struct device_node *node, struct device_node *parent);
|
||||
void gic_secondary_init(unsigned int);
|
||||
void gic_handle_irq(struct pt_regs *regs);
|
||||
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
|
||||
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
|
||||
|
||||
static inline void gic_init(unsigned int nr, int start,
|
||||
void __iomem *dist , void __iomem *cpu)
|
||||
{
|
||||
gic_init_bases(nr, start, dist, cpu, 0, NULL);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* arch/arm/include/asm/hardware/vic.h
|
||||
*
|
||||
* Copyright (c) ARM Limited 2003. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARM_HARDWARE_VIC_H
|
||||
#define __ASM_ARM_HARDWARE_VIC_H
|
||||
|
||||
#define VIC_IRQ_STATUS 0x00
|
||||
#define VIC_FIQ_STATUS 0x04
|
||||
#define VIC_RAW_STATUS 0x08
|
||||
#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
|
||||
#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
|
||||
#define VIC_INT_ENABLE_CLEAR 0x14
|
||||
#define VIC_INT_SOFT 0x18
|
||||
#define VIC_INT_SOFT_CLEAR 0x1c
|
||||
#define VIC_PROTECT 0x20
|
||||
#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
|
||||
#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
|
||||
|
||||
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
|
||||
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
|
||||
#define VIC_ITCR 0x300 /* VIC test control register */
|
||||
|
||||
#define VIC_VECT_CNTL_ENABLE (1 << 5)
|
||||
|
||||
#define VIC_PL192_VECT_ADDR 0xF00
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device_node;
|
||||
struct pt_regs;
|
||||
|
||||
void __vic_init(void __iomem *base, int irq_start, u32 vic_sources,
|
||||
u32 resume_sources, struct device_node *node);
|
||||
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
|
||||
int vic_of_init(struct device_node *node, struct device_node *parent);
|
||||
void vic_handle_irq(struct pt_regs *regs);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif
|
||||
@@ -22,6 +22,7 @@ extern int show_fiq_list(struct seq_file *, int);
|
||||
|
||||
#ifdef CONFIG_MULTI_IRQ_HANDLER
|
||||
extern void (*handle_arch_irq)(struct pt_regs *);
|
||||
extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
@@ -117,6 +117,16 @@ void __init init_IRQ(void)
|
||||
machine_desc->init_irq();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MULTI_IRQ_HANDLER
|
||||
void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
|
||||
{
|
||||
if (handle_arch_irq)
|
||||
return;
|
||||
|
||||
handle_arch_irq = handle_irq;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPARSE_IRQ
|
||||
int __init arch_probe_nr_irqs(void)
|
||||
{
|
||||
|
||||
@@ -416,7 +416,8 @@ static void (*smp_cross_call)(const struct cpumask *, unsigned int);
|
||||
|
||||
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
|
||||
{
|
||||
smp_cross_call = fn;
|
||||
if (!smp_cross_call)
|
||||
smp_cross_call = fn;
|
||||
}
|
||||
|
||||
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
|
||||
|
||||
@@ -24,7 +24,6 @@
|
||||
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
/* set up by the platform code */
|
||||
static void __iomem *twd_base;
|
||||
|
||||
@@ -11,22 +11,15 @@
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irqchip.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
static const struct of_device_id irq_match[] = {
|
||||
{.compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{}
|
||||
};
|
||||
|
||||
static void timer_init(void)
|
||||
{
|
||||
}
|
||||
@@ -35,11 +28,6 @@ static struct sys_timer timer = {
|
||||
.init = timer_init,
|
||||
};
|
||||
|
||||
static void __init init_irq(void)
|
||||
{
|
||||
of_irq_init(irq_match);
|
||||
}
|
||||
|
||||
static void __init board_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
||||
@@ -49,9 +37,8 @@ static void __init board_init(void)
|
||||
static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
|
||||
|
||||
DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
|
||||
.init_irq = init_irq,
|
||||
.init_irq = irqchip_init,
|
||||
.timer = &timer,
|
||||
.init_machine = board_init,
|
||||
.dt_compat = bcm11351_dt_compat,
|
||||
.handle_irq = gic_handle_irq,
|
||||
MACHINE_END
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
@@ -251,7 +250,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
|
||||
.map_io = cns3420_map_io,
|
||||
.init_irq = cns3xxx_init_irq,
|
||||
.timer = &cns3xxx_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = cns3420_init,
|
||||
.restart = cns3xxx_restart,
|
||||
MACHINE_END
|
||||
|
||||
@@ -12,10 +12,10 @@
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <mach/cns3xxx.h>
|
||||
#include "core.h"
|
||||
|
||||
@@ -17,7 +17,6 @@
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -39,7 +38,6 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = adssphere_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -34,6 +34,7 @@
|
||||
#include <linux/i2c-gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <linux/platform_data/video-ep93xx.h>
|
||||
@@ -44,8 +45,6 @@
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/*************************************************************************
|
||||
|
||||
@@ -39,7 +39,6 @@
|
||||
#include <linux/platform_data/spi-ep93xx.h>
|
||||
#include <mach/gpio-ep93xx.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -276,7 +275,6 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -290,7 +288,6 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -304,7 +301,6 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -318,7 +314,6 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -332,7 +327,6 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -346,7 +340,6 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -360,7 +353,6 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -374,7 +366,6 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = edb93xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -17,7 +17,6 @@
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -39,7 +38,6 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = gesbc9312_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -82,7 +81,6 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = micro9_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -96,7 +94,6 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = micro9_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -110,7 +107,6 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = micro9_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
@@ -124,7 +120,6 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = micro9_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <linux/platform_data/video-ep93xx.h>
|
||||
#include <mach/gpio-ep93xx.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -83,7 +82,6 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = simone_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -31,7 +31,6 @@
|
||||
#include <linux/platform_data/video-ep93xx.h>
|
||||
#include <mach/gpio-ep93xx.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -176,7 +175,6 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ep93xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = snappercl15_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -22,7 +22,6 @@
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -246,7 +245,6 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = ts72xx_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = ts72xx_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -34,7 +34,6 @@
|
||||
#include <linux/platform_data/spi-ep93xx.h>
|
||||
#include <mach/gpio-ep93xx.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -364,7 +363,6 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = vision_map_io,
|
||||
.init_irq = ep93xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &ep93xx_timer,
|
||||
.init_machine = vision_init_machine,
|
||||
.init_late = ep93xx_init_late,
|
||||
|
||||
@@ -22,12 +22,13 @@
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/exception.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/cacheflush.h>
|
||||
@@ -644,8 +645,6 @@ static int __init combiner_of_init(struct device_node *np,
|
||||
}
|
||||
|
||||
static const struct of_device_id exynos_dt_irq_match[] = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
|
||||
{ .compatible = "samsung,exynos4210-combiner",
|
||||
.data = combiner_of_init, },
|
||||
{},
|
||||
@@ -661,8 +660,10 @@ void __init exynos4_init_irq(void)
|
||||
if (!of_have_populated_dt())
|
||||
gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
|
||||
#ifdef CONFIG_OF
|
||||
else
|
||||
else {
|
||||
irqchip_init();
|
||||
of_irq_init(exynos_dt_irq_match);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (!of_have_populated_dt())
|
||||
@@ -679,6 +680,7 @@ void __init exynos4_init_irq(void)
|
||||
void __init exynos5_init_irq(void)
|
||||
{
|
||||
#ifdef CONFIG_OF
|
||||
irqchip_init();
|
||||
of_irq_init(exynos_dt_irq_match);
|
||||
#endif
|
||||
/*
|
||||
|
||||
@@ -13,7 +13,7 @@
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */
|
||||
|
||||
@@ -16,7 +16,6 @@
|
||||
#include <linux/smsc911x.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
@@ -201,7 +200,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = armlex4210_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -15,7 +15,6 @@
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
@@ -107,7 +106,6 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = exynos4_dt_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -16,7 +16,6 @@
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
@@ -179,7 +178,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
|
||||
.init_irq = exynos5_init_irq,
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.map_io = exynos5_dt_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = exynos5_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -39,7 +39,6 @@
|
||||
#include <media/v4l2-mediabus.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/adc.h>
|
||||
@@ -1379,7 +1378,6 @@ MACHINE_START(NURI, "NURI")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = nuri_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = nuri_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <linux/platform_data/usb-exynos.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
@@ -814,7 +813,6 @@ MACHINE_START(ORIGEN, "ORIGEN")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = origen_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = origen_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <linux/platform_data/s3c-hsotg.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/samsung_fimd.h>
|
||||
@@ -376,7 +375,6 @@ MACHINE_START(SMDK4212, "SMDK4212")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
.restart = exynos4_restart,
|
||||
@@ -390,7 +388,6 @@ MACHINE_START(SMDK4412, "SMDK4412")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -26,7 +26,6 @@
|
||||
#include <linux/platform_data/usb-exynos.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
@@ -423,7 +422,6 @@ MACHINE_START(SMDKV310, "SMDKV310")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
.reserve = &smdkv310_reserve,
|
||||
@@ -436,7 +434,6 @@ MACHINE_START(SMDKC210, "SMDKC210")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &exynos4_timer,
|
||||
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <drm/exynos_drm.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/samsung_fimd.h>
|
||||
@@ -1151,7 +1150,6 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = universal_map_io,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = universal_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -22,7 +22,6 @@
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/arch_timer.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/localtimer.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
@@ -20,9 +20,9 @@
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
@@ -149,7 +149,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
|
||||
|
||||
__raw_writel(virt_to_phys(exynos4_secondary_startup),
|
||||
cpu_boot_reg(phys_cpu));
|
||||
gic_raise_softirq(cpumask_of(cpu), 0);
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
if (pen_release == -1)
|
||||
break;
|
||||
@@ -190,8 +190,6 @@ static void __init exynos_smp_init_cpus(void)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
@@ -32,7 +33,6 @@
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/timer-sp.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -66,12 +66,6 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
|
||||
HB_JUMP_TABLE_PHYS(cpu) + 15);
|
||||
}
|
||||
|
||||
const static struct of_device_id irq_match[] = {
|
||||
{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{}
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static void highbank_l2x0_disable(void)
|
||||
{
|
||||
@@ -82,7 +76,7 @@ static void highbank_l2x0_disable(void)
|
||||
|
||||
static void __init highbank_init_irq(void)
|
||||
{
|
||||
of_irq_init(irq_match);
|
||||
irqchip_init();
|
||||
|
||||
if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
|
||||
highbank_scu_map_io();
|
||||
@@ -210,7 +204,6 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
|
||||
.map_io = debug_ll_io_init,
|
||||
.init_irq = highbank_init_irq,
|
||||
.timer = &highbank_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = highbank_init,
|
||||
.dt_compat = highbank_match,
|
||||
.restart = highbank_restart,
|
||||
|
||||
@@ -17,9 +17,9 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include "core.h"
|
||||
|
||||
@@ -33,7 +33,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
|
||||
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
highbank_set_cpu_jump(cpu, secondary_startup);
|
||||
gic_raise_softirq(cpumask_of(cpu), 0);
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -56,8 +56,6 @@ static void __init highbank_smp_init_cpus(void)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
|
||||
|
||||
@@ -112,7 +112,6 @@ void tzic_handle_irq(struct pt_regs *);
|
||||
#define imx50_handle_irq tzic_handle_irq
|
||||
#define imx51_handle_irq tzic_handle_irq
|
||||
#define imx53_handle_irq tzic_handle_irq
|
||||
#define imx6q_handle_irq gic_handle_irq
|
||||
|
||||
extern void imx_enable_cpu(int cpu, bool enable);
|
||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#define GPC_IMR1 0x008
|
||||
#define GPC_PGC_CPU_PDN 0x2a0
|
||||
|
||||
@@ -18,6 +18,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
@@ -29,7 +30,6 @@
|
||||
#include <asm/cpuidle.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/system_misc.h>
|
||||
@@ -221,17 +221,12 @@ static void __init imx6q_map_io(void)
|
||||
imx6q_clock_map_io();
|
||||
}
|
||||
|
||||
static const struct of_device_id imx6q_irq_match[] __initconst = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx6q_init_irq(void)
|
||||
{
|
||||
l2x0_of_init(0, ~0UL);
|
||||
imx_src_init();
|
||||
imx_gpc_init();
|
||||
of_irq_init(imx6q_irq_match);
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static void __init imx6q_timer_init(void)
|
||||
@@ -254,7 +249,6 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
|
||||
.smp = smp_ops(imx_smp_ops),
|
||||
.map_io = imx6q_map_io,
|
||||
.init_irq = imx6q_init_irq,
|
||||
.handle_irq = imx6q_handle_irq,
|
||||
.timer = &imx6q_timer,
|
||||
.init_machine = imx6q_init_machine,
|
||||
.init_late = imx6q_init_late,
|
||||
|
||||
@@ -12,9 +12,9 @@
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
@@ -71,8 +71,6 @@ static void __init imx_smp_init_cpus(void)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
void imx_smp_prepare(void)
|
||||
|
||||
@@ -11,26 +11,15 @@
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include "common.h"
|
||||
|
||||
static const struct of_device_id msm_dt_gic_match[] __initconst = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init msm8x60_init_irq(void)
|
||||
{
|
||||
of_irq_init(msm_dt_gic_match);
|
||||
}
|
||||
|
||||
static void __init msm8x60_init_late(void)
|
||||
{
|
||||
smd_debugfs_init();
|
||||
@@ -55,8 +44,7 @@ static const char *msm8x60_fluid_match[] __initdata = {
|
||||
DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
|
||||
.smp = smp_ops(msm_smp_ops),
|
||||
.map_io = msm_map_msm8x60_io,
|
||||
.init_irq = msm8x60_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_irq = irqchip_init,
|
||||
.init_machine = msm8x60_dt_init,
|
||||
.init_late = msm8x60_init_late,
|
||||
.timer = &msm_dt_timer,
|
||||
|
||||
@@ -11,24 +11,13 @@
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static const struct of_device_id msm_dt_gic_match[] __initconst = {
|
||||
{ .compatible = "qcom,msm-qgic2", .data = gic_of_init },
|
||||
{ }
|
||||
};
|
||||
|
||||
static void __init msm_dt_init_irq(void)
|
||||
{
|
||||
of_irq_init(msm_dt_gic_match);
|
||||
}
|
||||
|
||||
static void __init msm_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
@@ -42,9 +31,8 @@ static const char * const msm8960_dt_match[] __initconst = {
|
||||
DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
|
||||
.smp = smp_ops(msm_smp_ops),
|
||||
.map_io = msm_map_msm8960_io,
|
||||
.init_irq = msm_dt_init_irq,
|
||||
.init_irq = irqchip_init,
|
||||
.timer = &msm_dt_timer,
|
||||
.init_machine = msm_dt_init,
|
||||
.dt_compat = msm8960_dt_match,
|
||||
.handle_irq = gic_handle_irq,
|
||||
MACHINE_END
|
||||
|
||||
@@ -15,8 +15,8 @@
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/mach-types.h>
|
||||
@@ -115,7 +115,7 @@ static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *id
|
||||
* the boot monitor to read the system wide flags register,
|
||||
* and branch to the address found there.
|
||||
*/
|
||||
gic_raise_softirq(cpumask_of(cpu), 0);
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
@@ -153,8 +153,6 @@ static void __init msm_smp_init_cpus(void)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
||||
|
||||
@@ -23,9 +23,9 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <mach/netx-regs.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <mach/netx-regs.h>
|
||||
#include <linux/platform_data/eth-netx.h>
|
||||
|
||||
@@ -204,7 +203,6 @@ MACHINE_START(NXDB500, "Hilscher nxdb500")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = netx_map_io,
|
||||
.init_irq = netx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &netx_timer,
|
||||
.init_machine = nxdb500_init,
|
||||
.restart = netx_restart,
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <mach/netx-regs.h>
|
||||
#include <linux/platform_data/eth-netx.h>
|
||||
|
||||
@@ -97,7 +96,6 @@ MACHINE_START(NXDKN, "Hilscher nxdkn")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = netx_map_io,
|
||||
.init_irq = netx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &netx_timer,
|
||||
.init_machine = nxdkn_init,
|
||||
.restart = netx_restart,
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <mach/netx-regs.h>
|
||||
#include <linux/platform_data/eth-netx.h>
|
||||
|
||||
@@ -181,7 +180,6 @@ MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = netx_map_io,
|
||||
.init_irq = netx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &netx_timer,
|
||||
.init_machine = nxeb500hmi_init,
|
||||
.restart = netx_restart,
|
||||
|
||||
@@ -27,7 +27,6 @@
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
#include <linux/platform_data/clocksource-nomadik-mtu.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -352,7 +351,6 @@ MACHINE_START(NOMADIK, "NHK8815")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = cpu8815_map_io,
|
||||
.init_irq = cpu8815_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &nomadik_timer,
|
||||
.init_machine = nhk8815_platform_init,
|
||||
.restart = cpu8815_restart,
|
||||
|
||||
@@ -25,13 +25,13 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
#include <linux/platform_data/clk-nomadik.h>
|
||||
#include <linux/platform_data/pinctrl-nomadik.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
@@ -26,10 +26,10 @@
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/leds_pwm.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/omap4-keypad.h>
|
||||
#include <linux/usb/musb.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -722,7 +722,6 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
|
||||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = omap_4430sdp_init,
|
||||
.init_late = omap4430_init_late,
|
||||
.timer = &omap4_timer,
|
||||
|
||||
@@ -16,7 +16,6 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
@@ -156,7 +155,6 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
|
||||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = omap_gic_of_init,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.init_late = omap4430_init_late,
|
||||
.timer = &omap4_timer,
|
||||
@@ -177,7 +175,6 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
|
||||
.map_io = omap5_map_io,
|
||||
.init_early = omap5_init_early,
|
||||
.init_irq = omap_gic_of_init,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.timer = &omap5_timer,
|
||||
.dt_compat = omap5_boards_compat,
|
||||
|
||||
@@ -31,9 +31,9 @@
|
||||
#include <linux/ti_wilink_st.h>
|
||||
#include <linux/usb/musb.h>
|
||||
#include <linux/wl12xx.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/omap-abe-twl6040.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -459,7 +459,6 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
|
||||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = omap4_panda_init,
|
||||
.init_late = omap4430_init_late,
|
||||
.timer = &omap4_timer,
|
||||
|
||||
@@ -19,9 +19,9 @@
|
||||
#include <linux/device.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include "omap-secure.h"
|
||||
@@ -157,7 +157,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
|
||||
booted = true;
|
||||
}
|
||||
|
||||
gic_raise_softirq(cpumask_of(cpu), 0);
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
|
||||
/*
|
||||
* Now the secondary core is starting up let it run its
|
||||
@@ -231,8 +231,6 @@ static void __init omap4_smp_init_cpus(void)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
|
||||
|
||||
@@ -24,8 +24,7 @@
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/cpu_pm.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include "omap-wakeupgen.h"
|
||||
#include "omap-secure.h"
|
||||
|
||||
@@ -15,13 +15,14 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/memblock.h>
|
||||
@@ -255,16 +256,10 @@ static int __init omap4_sar_ram_init(void)
|
||||
}
|
||||
early_initcall(omap4_sar_ram_init);
|
||||
|
||||
static struct of_device_id irq_match[] __initdata = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
|
||||
{ }
|
||||
};
|
||||
|
||||
void __init omap_gic_of_init(void)
|
||||
{
|
||||
omap_wakeupgen_init();
|
||||
of_irq_init(irq_match);
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
|
||||
|
||||
@@ -9,6 +9,7 @@
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
@@ -17,7 +18,6 @@
|
||||
#include <linux/dw_apb_timer.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
@@ -70,16 +70,6 @@ static const char *picoxcell_dt_match[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
static const struct of_device_id vic_of_match[] __initconst = {
|
||||
{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static void __init picoxcell_init_irq(void)
|
||||
{
|
||||
of_irq_init(vic_of_match);
|
||||
}
|
||||
|
||||
static void picoxcell_wdt_restart(char mode, const char *cmd)
|
||||
{
|
||||
/*
|
||||
@@ -97,8 +87,7 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
|
||||
DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
|
||||
.map_io = picoxcell_map_io,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = picoxcell_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.init_irq = irqchip_init,
|
||||
.timer = &dw_apb_timer,
|
||||
.init_machine = picoxcell_init_machine,
|
||||
.dt_compat = picoxcell_dt_match,
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <mach/platform.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
@@ -14,7 +14,6 @@
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
@@ -59,8 +58,6 @@ static void __init realview_smp_init_cpus(void)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
|
||||
|
||||
@@ -27,13 +27,13 @@
|
||||
#include <linux/amba/mmci.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/clk-realview.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
||||
@@ -473,7 +473,6 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
|
||||
.init_early = realview_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.timer = &realview_eb_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = realview_eb_init,
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
.dma_zone_size = SZ_256M,
|
||||
|
||||
@@ -29,13 +29,13 @@
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/clk-realview.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -385,7 +385,6 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
|
||||
.init_early = realview_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.timer = &realview_pb1176_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = realview_pb1176_init,
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
.dma_zone_size = SZ_256M,
|
||||
|
||||
@@ -27,13 +27,13 @@
|
||||
#include <linux/amba/mmci.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/clk-realview.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
||||
@@ -368,7 +368,6 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
|
||||
.init_early = realview_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.timer = &realview_pb11mp_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = realview_pb11mp_init,
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
.dma_zone_size = SZ_256M,
|
||||
|
||||
@@ -27,12 +27,12 @@
|
||||
#include <linux/amba/mmci.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/clk-realview.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -309,7 +309,6 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
|
||||
.init_early = realview_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.timer = &realview_pba8_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = realview_pba8_init,
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
.dma_zone_size = SZ_256M,
|
||||
|
||||
@@ -26,13 +26,13 @@
|
||||
#include <linux/amba/mmci.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/clk-realview.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
@@ -405,7 +405,6 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
|
||||
.init_early = realview_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.timer = &realview_pbx_timer,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = realview_pbx_init,
|
||||
#ifdef CONFIG_ZONE_DMA
|
||||
.dma_zone_size = SZ_256M,
|
||||
|
||||
@@ -25,10 +25,10 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
@@ -15,6 +15,5 @@
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
|
||||
|
||||
@@ -15,6 +15,8 @@
|
||||
#ifndef __ASM_ARCH_TICK_H
|
||||
#define __ASM_ARCH_TICK_H __FILE__
|
||||
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
|
||||
/* note, the timer interrutps turn up in 2 places, the vic and then
|
||||
* the timer block. We take the VIC as the base at the moment.
|
||||
*/
|
||||
|
||||
@@ -31,7 +31,6 @@
|
||||
#include <video/platform_lcd.h>
|
||||
#include <video/samsung_fimd.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
@@ -230,7 +229,6 @@ MACHINE_START(ANW6410, "A&W6410")
|
||||
.atag_offset = 0x100,
|
||||
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = anw6410_map_io,
|
||||
.init_machine = anw6410_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
|
||||
#include <sound/wm1250-ev1.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
@@ -867,7 +866,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
|
||||
/* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = crag6410_map_io,
|
||||
.init_machine = crag6410_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -30,7 +30,6 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
@@ -273,7 +272,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
|
||||
/* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = hmt_map_io,
|
||||
.init_machine = hmt_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -24,7 +24,6 @@
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -352,7 +351,6 @@ MACHINE_START(MINI6410, "MINI6410")
|
||||
/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = mini6410_map_io,
|
||||
.init_machine = mini6410_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -26,7 +26,6 @@
|
||||
#include <video/platform_lcd.h>
|
||||
#include <video/samsung_fimd.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
@@ -101,7 +100,6 @@ MACHINE_START(NCP, "NCP")
|
||||
/* Maintainer: Samsung Electronics */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = ncp_map_io,
|
||||
.init_machine = ncp_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -331,7 +330,6 @@ MACHINE_START(REAL6410, "REAL6410")
|
||||
.atag_offset = 0x100,
|
||||
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = real6410_map_io,
|
||||
.init_machine = real6410_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -17,7 +17,6 @@
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -153,7 +152,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
|
||||
/* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smartq_map_io,
|
||||
.init_machine = smartq5_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -17,7 +17,6 @@
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
@@ -169,7 +168,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
|
||||
/* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smartq_map_io,
|
||||
.init_machine = smartq7_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -22,7 +22,6 @@
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
@@ -90,7 +89,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
|
||||
.atag_offset = 0x100,
|
||||
|
||||
.init_irq = s3c6400_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdk6400_map_io,
|
||||
.init_machine = smdk6400_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -45,7 +45,6 @@
|
||||
#include <video/platform_lcd.h>
|
||||
#include <video/samsung_fimd.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
@@ -700,7 +699,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
|
||||
.atag_offset = 0x100,
|
||||
|
||||
.init_irq = s3c6410_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdk6410_map_io,
|
||||
.init_machine = smdk6410_machine_init,
|
||||
.init_late = s3c64xx_init_late,
|
||||
|
||||
@@ -13,7 +13,6 @@
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */
|
||||
|
||||
@@ -1,29 +0,0 @@
|
||||
/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
|
||||
*
|
||||
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S5P64X0 - Timer tick support definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_TICK_H
|
||||
#define __ASM_ARCH_TICK_H __FILE__
|
||||
|
||||
static inline u32 s3c24xx_ostimer_pending(void)
|
||||
{
|
||||
u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
|
||||
return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
|
||||
}
|
||||
|
||||
#define TICK_MAX (0xffffffff)
|
||||
|
||||
#endif /* __ASM_ARCH_TICK_H */
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <video/platform_lcd.h>
|
||||
#include <video/samsung_fimd.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/irq.h>
|
||||
@@ -272,7 +271,6 @@ MACHINE_START(SMDK6440, "SMDK6440")
|
||||
.atag_offset = 0x100,
|
||||
|
||||
.init_irq = s5p6440_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdk6440_map_io,
|
||||
.init_machine = smdk6440_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <video/platform_lcd.h>
|
||||
#include <video/samsung_fimd.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/irq.h>
|
||||
@@ -291,7 +290,6 @@ MACHINE_START(SMDK6450, "SMDK6450")
|
||||
.atag_offset = 0x100,
|
||||
|
||||
.init_irq = s5p6450_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdk6450_map_io,
|
||||
.init_machine = smdk6450_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -14,6 +14,5 @@
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */
|
||||
|
||||
@@ -15,6 +15,8 @@
|
||||
#ifndef __ASM_ARCH_TICK_H
|
||||
#define __ASM_ARCH_TICK_H __FILE__
|
||||
|
||||
#include <linux/irqchip/arm-vic.h>
|
||||
|
||||
/* note, the timer interrutps turn up in 2 places, the vic and then
|
||||
* the timer block. We take the VIC as the base at the moment.
|
||||
*/
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <linux/input.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
@@ -254,7 +253,6 @@ MACHINE_START(SMDKC100, "SMDKC100")
|
||||
/* Maintainer: Byungho Min <bhmin@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s5pc100_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdkc100_map_io,
|
||||
.init_machine = smdkc100_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
|
||||
@@ -13,7 +13,6 @@
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H
|
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */
|
||||
|
||||
@@ -1,26 +0,0 @@
|
||||
/* linux/arch/arm/mach-s5pv210/include/mach/tick.h
|
||||
*
|
||||
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Based on arch/arm/mach-s3c6400/include/mach/tick.h
|
||||
*
|
||||
* S5PV210 - Timer tick support definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_TICK_H
|
||||
#define __ASM_ARCH_TICK_H __FILE__
|
||||
|
||||
static inline u32 s3c24xx_ostimer_pending(void)
|
||||
{
|
||||
u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
|
||||
return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
|
||||
}
|
||||
|
||||
#define TICK_MAX (0xffffffff)
|
||||
|
||||
#endif /* __ASM_ARCH_TICK_H */
|
||||
@@ -22,7 +22,6 @@
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/setup.h>
|
||||
@@ -685,7 +684,6 @@ MACHINE_START(AQUILA, "Aquila")
|
||||
Kyungmin Park <kyungmin.park@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s5pv210_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = aquila_map_io,
|
||||
.init_machine = aquila_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -29,7 +29,6 @@
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_data/s3c-hsotg.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/setup.h>
|
||||
@@ -972,7 +971,6 @@ MACHINE_START(GONI, "GONI")
|
||||
/* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s5pv210_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = goni_map_io,
|
||||
.init_machine = goni_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -15,7 +15,6 @@
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/setup.h>
|
||||
@@ -152,7 +151,6 @@ MACHINE_START(SMDKC110, "SMDKC110")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s5pv210_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdkc110_map_io,
|
||||
.init_machine = smdkc110_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -21,7 +21,6 @@
|
||||
#include <linux/pwm_backlight.h>
|
||||
#include <linux/platform_data/s3c-hsotg.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/setup.h>
|
||||
@@ -328,7 +327,6 @@ MACHINE_START(SMDKV210, "SMDKV210")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s5pv210_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = smdkv210_map_io,
|
||||
.init_machine = smdkv210_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -14,7 +14,6 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/setup.h>
|
||||
@@ -129,7 +128,6 @@ MACHINE_START(TORBRECK, "TORBRECK")
|
||||
/* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = s5pv210_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.map_io = torbreck_map_io,
|
||||
.init_machine = torbreck_machine_init,
|
||||
.timer = &s5p_timer,
|
||||
|
||||
@@ -40,6 +40,7 @@
|
||||
#include <linux/mmc/sh_mobile_sdhi.h>
|
||||
#include <linux/mfd/tmio.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <video/sh_mobile_lcdc.h>
|
||||
#include <video/sh_mipi_dsi.h>
|
||||
#include <sound/sh_fsi.h>
|
||||
@@ -49,7 +50,6 @@
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
@@ -668,7 +668,6 @@ MACHINE_START(AG5EVM, "ag5evm")
|
||||
.init_early = sh73a0_add_early_devices,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = sh73a0_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = ag5evm_init,
|
||||
.init_late = shmobile_init_late,
|
||||
.timer = &shmobile_timer,
|
||||
|
||||
@@ -35,6 +35,7 @@
|
||||
#include <linux/input/sh_keysc.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/leds-renesas-tpu.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sh_mmcif.h>
|
||||
@@ -47,7 +48,6 @@
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
@@ -550,7 +550,6 @@ MACHINE_START(KOTA2, "kota2")
|
||||
.init_early = sh73a0_add_early_devices,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = sh73a0_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = kota2_init,
|
||||
.init_late = shmobile_init_late,
|
||||
.timer = &shmobile_timer,
|
||||
|
||||
@@ -28,7 +28,6 @@
|
||||
#include <mach/emev2.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
/* Dummy supplies, where voltage doesn't matter */
|
||||
static struct regulator_consumer_supply dummy_supplies[] = {
|
||||
@@ -89,7 +88,6 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
|
||||
.init_early = emev2_add_early_devices,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = emev2_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = kzm9d_add_standard_devices,
|
||||
.init_late = shmobile_init_late,
|
||||
.timer = &shmobile_timer,
|
||||
|
||||
@@ -25,6 +25,7 @@
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/pcf857x.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/sh_mmcif.h>
|
||||
#include <linux/mmc/sh_mobile_sdhi.h>
|
||||
@@ -42,7 +43,6 @@
|
||||
#include <mach/sh73a0.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <video/sh_mobile_lcdc.h>
|
||||
@@ -792,7 +792,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
|
||||
.init_early = sh73a0_add_early_devices,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = sh73a0_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = kzm_init,
|
||||
.init_late = shmobile_init_late,
|
||||
.timer = &shmobile_timer,
|
||||
|
||||
@@ -44,7 +44,6 @@
|
||||
#include <mach/irqs.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
/* Fixed 3.3V regulator to be used by SDHI0 */
|
||||
@@ -382,7 +381,6 @@ MACHINE_START(MARZEN, "marzen")
|
||||
.init_early = r8a7779_add_early_devices,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = r8a7779_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = marzen_init,
|
||||
.init_late = marzen_init_late,
|
||||
.timer = &shmobile_timer,
|
||||
|
||||
@@ -22,10 +22,10 @@
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
|
||||
@@ -23,10 +23,10 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/sh73a0.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
|
||||
@@ -12,7 +12,6 @@
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
void __init shmobile_smp_init_cpus(unsigned int ncores)
|
||||
{
|
||||
@@ -26,6 +25,4 @@ void __init shmobile_smp_init_cpus(unsigned int ncores)
|
||||
|
||||
for (i = 0; i < ncores; i++)
|
||||
set_cpu_possible(i, true);
|
||||
|
||||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
@@ -20,13 +20,14 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/gpio-em.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/emev2.h>
|
||||
@@ -35,7 +36,6 @@
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
static struct map_desc emev2_io_desc[] __initdata = {
|
||||
#ifdef CONFIG_SMP
|
||||
@@ -445,27 +445,16 @@ void __init emev2_add_standard_devices_dt(void)
|
||||
emev2_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static const struct of_device_id emev2_dt_irq_match[] = {
|
||||
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||
{},
|
||||
};
|
||||
|
||||
static const char *emev2_boards_compat_dt[] __initdata = {
|
||||
"renesas,emev2",
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init emev2_init_irq_dt(void)
|
||||
{
|
||||
of_irq_init(emev2_dt_irq_match);
|
||||
}
|
||||
|
||||
DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
|
||||
.smp = smp_ops(emev2_smp_ops),
|
||||
.init_early = emev2_init_delay,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = emev2_init_irq_dt,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_irq = irqchip_init,
|
||||
.init_machine = emev2_add_standard_devices_dt,
|
||||
.timer = &shmobile_timer,
|
||||
.dt_compat = emev2_boards_compat_dt,
|
||||
|
||||
Некоторые файлы не были показаны из-за слишком большого количества измененных файлов Показать больше
Ссылка в новой задаче
Block a user