POWERPC: Allow 32-bit hashed pgtable code to support 36-bit physical
This rearranges a bit of code, and adds support for 36-bit physical addressing for configs that use a hashed page table. The 36b physical support is not enabled by default on any config - it must be explicitly enabled via the config system. This patch *only* expands the page table code to accomodate large physical addresses on 32-bit systems and enables the PHYS_64BIT config option for 86xx. It does *not* allow you to boot a board with more than about 3.5GB of RAM - for that, SWIOTLB support is also required (and coming soon). Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Becky Bruce
@@ -75,7 +75,7 @@ _GLOBAL(hash_page_sync)
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* Returns to the caller if the access is illegal or there is no
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* mapping for the address. Otherwise it places an appropriate PTE
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* in the hash table and returns from the exception.
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* Uses r0, r3 - r8, ctr, lr.
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* Uses r0, r3 - r8, r10, ctr, lr.
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*/
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.text
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_GLOBAL(hash_page)
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@@ -106,9 +106,15 @@ _GLOBAL(hash_page)
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addi r5,r5,swapper_pg_dir@l /* kernel page table */
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rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
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112: add r5,r5,r7 /* convert to phys addr */
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#ifndef CONFIG_PTE_64BIT
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rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
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lwz r8,0(r5) /* get pmd entry */
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rlwinm. r8,r8,0,0,19 /* extract address of pte page */
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#else
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rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
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lwzx r8,r8,r5 /* Get L1 entry */
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rlwinm. r8,r8,0,0,20 /* extract pt base address */
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#endif
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#ifdef CONFIG_SMP
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beq- hash_page_out /* return if no mapping */
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#else
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@@ -118,7 +124,11 @@ _GLOBAL(hash_page)
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to the address following the rfi. */
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beqlr-
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#endif
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#ifndef CONFIG_PTE_64BIT
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rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
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#else
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rlwimi r8,r4,23,20,28 /* compute pte address */
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#endif
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rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
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ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
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@@ -127,9 +137,15 @@ _GLOBAL(hash_page)
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* because almost always, there won't be a permission violation
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* and there won't already be an HPTE, and thus we will have
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* to update the PTE to set _PAGE_HASHPTE. -- paulus.
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*
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* If PTE_64BIT is set, the low word is the flags word; use that
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* word for locking since it contains all the interesting bits.
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*/
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#if (PTE_FLAGS_OFFSET != 0)
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addi r8,r8,PTE_FLAGS_OFFSET
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#endif
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retry:
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lwarx r6,0,r8 /* get linux-style pte */
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lwarx r6,0,r8 /* get linux-style pte, flag word */
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andc. r5,r3,r6 /* check access & ~permission */
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#ifdef CONFIG_SMP
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bne- hash_page_out /* return if access not permitted */
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@@ -137,6 +153,15 @@ retry:
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bnelr-
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#endif
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or r5,r0,r6 /* set accessed/dirty bits */
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_SMP
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subf r10,r6,r8 /* create false data dependency */
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subi r10,r10,PTE_FLAGS_OFFSET
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lwzx r10,r6,r10 /* Get upper PTE word */
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#else
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lwz r10,-PTE_FLAGS_OFFSET(r8)
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_PTE_64BIT */
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stwcx. r5,0,r8 /* attempt to update PTE */
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bne- retry /* retry if someone got there first */
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@@ -203,9 +228,9 @@ _GLOBAL(add_hash_page)
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* we can't take a hash table miss (assuming the code is
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* covered by a BAT). -- paulus
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*/
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mfmsr r10
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mfmsr r9
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear MSR_DR */
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mtmsr r0
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SYNC_601
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@@ -214,14 +239,14 @@ _GLOBAL(add_hash_page)
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tophys(r7,0)
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#ifdef CONFIG_SMP
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addis r9,r7,mmu_hash_lock@ha
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addi r9,r9,mmu_hash_lock@l
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10: lwarx r0,0,r9 /* take the mmu_hash_lock */
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addis r6,r7,mmu_hash_lock@ha
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addi r6,r6,mmu_hash_lock@l
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10: lwarx r0,0,r6 /* take the mmu_hash_lock */
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cmpi 0,r0,0
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bne- 11f
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stwcx. r8,0,r9
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stwcx. r8,0,r6
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beq+ 12f
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11: lwz r0,0(r9)
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11: lwz r0,0(r6)
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cmpi 0,r0,0
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beq 10b
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b 11b
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@@ -234,10 +259,24 @@ _GLOBAL(add_hash_page)
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* HPTE, so we just unlock and return.
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*/
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mr r8,r5
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#ifndef CONFIG_PTE_64BIT
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rlwimi r8,r4,22,20,29
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#else
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rlwimi r8,r4,23,20,28
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addi r8,r8,PTE_FLAGS_OFFSET
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#endif
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1: lwarx r6,0,r8
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andi. r0,r6,_PAGE_HASHPTE
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bne 9f /* if HASHPTE already set, done */
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_SMP
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subf r10,r6,r8 /* create false data dependency */
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subi r10,r10,PTE_FLAGS_OFFSET
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lwzx r10,r6,r10 /* Get upper PTE word */
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#else
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lwz r10,-PTE_FLAGS_OFFSET(r8)
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_PTE_64BIT */
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ori r5,r6,_PAGE_HASHPTE
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stwcx. r5,0,r8
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bne- 1b
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@@ -246,13 +285,15 @@ _GLOBAL(add_hash_page)
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9:
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#ifdef CONFIG_SMP
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addis r6,r7,mmu_hash_lock@ha
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addi r6,r6,mmu_hash_lock@l
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eieio
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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stw r0,0(r6) /* clear mmu_hash_lock */
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#endif
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/* reenable interrupts and DR */
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mtmsr r10
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mtmsr r9
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SYNC_601
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isync
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@@ -267,7 +308,8 @@ _GLOBAL(add_hash_page)
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* r5 contains the linux PTE, r6 contains the old value of the
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* linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
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* offset to be added to addresses (0 if the MMU is on,
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* -KERNELBASE if it is off).
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* -KERNELBASE if it is off). r10 contains the upper half of
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* the PTE if CONFIG_PTE_64BIT.
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* On SMP, the caller should have the mmu_hash_lock held.
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* We assume that the caller has (or will) set the _PAGE_HASHPTE
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* bit in the linux PTE in memory. The value passed in r6 should
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@@ -313,6 +355,11 @@ _GLOBAL(create_hpte)
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BEGIN_FTR_SECTION
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ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
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#ifdef CONFIG_PTE_64BIT
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/* Put the XPN bits into the PTE */
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rlwimi r8,r10,8,20,22
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rlwimi r8,r10,2,29,29
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#endif
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/* Construct the high word of the PPC-style PTE (r5) */
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rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
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@@ -499,14 +546,18 @@ _GLOBAL(flush_hash_pages)
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isync
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/* First find a PTE in the range that has _PAGE_HASHPTE set */
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#ifndef CONFIG_PTE_64BIT
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rlwimi r5,r4,22,20,29
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1: lwz r0,0(r5)
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#else
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rlwimi r5,r4,23,20,28
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#endif
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1: lwz r0,PTE_FLAGS_OFFSET(r5)
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cmpwi cr1,r6,1
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andi. r0,r0,_PAGE_HASHPTE
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bne 2f
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ble cr1,19f
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addi r4,r4,0x1000
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addi r5,r5,4
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addi r5,r5,PTE_SIZE
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addi r6,r6,-1
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b 1b
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@@ -545,7 +596,10 @@ _GLOBAL(flush_hash_pages)
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* already clear, we're done (for this pte). If not,
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* clear it (atomically) and proceed. -- paulus.
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*/
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33: lwarx r8,0,r5 /* fetch the pte */
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#if (PTE_FLAGS_OFFSET != 0)
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addi r5,r5,PTE_FLAGS_OFFSET
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#endif
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33: lwarx r8,0,r5 /* fetch the pte flags word */
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andi. r0,r8,_PAGE_HASHPTE
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beq 8f /* done if HASHPTE is already clear */
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rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
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@@ -590,7 +644,7 @@ _GLOBAL(flush_hash_patch_B)
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8: ble cr1,9f /* if all ptes checked */
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81: addi r6,r6,-1
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addi r5,r5,4 /* advance to next pte */
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addi r5,r5,PTE_SIZE
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addi r4,r4,0x1000
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lwz r0,0(r5) /* check next pte */
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cmpwi cr1,r6,1
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