Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
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@@ -21,5 +21,15 @@
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#define CLKID_ZERO 13
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#define CLKID_MPEG_SEL 14
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#define CLKID_MPEG_DIV 15
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_SDIO 30
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#define CLKID_ETH 36
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_SANA 69
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#endif /* __MESON8B_CLKC_H */
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