xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mfd: db8500 OPP and sleep handling update

Browse Source 
This updates the operating point handling code by:

- Supporting the DDR OPP retention state.
- Supporting another low operating point named
  APE_50_PARTLY_25_OPP
- Adding an interface to figure out if the sleep state change
  was properly achieved.

Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Mattias Nilsson
2012-01-13 16:20:43 +01:00
committed by Samuel Ortiz
parent 992b133a5d
commit 4d64d2e34b
3 changed files with 110 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
include/linux/mfd/db8500-prcmu.h
View File

@@ -457,6 +457,25 @@ enum hw_acc_dev {
NUM_HW_ACC
};
/**
* enum prcmu_power_status - results from set_power_state
* @PRCMU_SLEEP_OK: Sleep went ok
* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
* @PRCMU_IDLE_OK: Idle went ok
* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
*
*/
enum prcmu_power_status {
PRCMU_SLEEP_OK = 0xf3,
PRCMU_DEEP_SLEEP_OK = 0xf6,
PRCMU_IDLE_OK = 0xf0,
PRCMU_DEEPIDLE_OK = 0xe3,
PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
PRCMU_ARMPENDINGIT_ER = 0x93,
};
/*
* Definitions for autonomous power management configuration.
*/
@@ -544,6 +563,7 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val);
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
@@ -699,6 +719,11 @@ static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
return 0;
}
static inline u8 db8500_prcmu_get_power_state_result(void)
{
return 0;
}
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)

15
include/linux/mfd/dbx500-prcmu.h
View File

@@ -185,12 +185,14 @@ enum prcmu_clock {
* @APE_NO_CHANGE: The APE operating point is unchanged
* @APE_100_OPP: The new APE operating point is ape100opp
* @APE_50_OPP: 50%
* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
*/
enum ape_opp {
APE_OPP_INIT = 0x00,
APE_NO_CHANGE = 0x01,
APE_100_OPP = 0x02,
APE_50_OPP = 0x03
APE_50_OPP = 0x03,
APE_50_PARTLY_25_OPP = 0xFF,
};
/**
@@ -271,6 +273,14 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
keep_ap_pll);
}
static inline u8 prcmu_get_power_state_result(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_power_state_result();
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
if (cpu_is_u5500())
@@ -663,9 +673,10 @@ static inline int prcmu_stop_temp_sense(void)
/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1
#ifdef CONFIG_UX500_PRCMU_QOS_POWER
#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);