scsi: be2iscsi: Fix POST check and reset sequence
SLIPORT FUNCTION_RESET does not reset the chip. So POST status needs to be checked before issuing FUNCTION_RESET. The completion of FUNCTION_RESET is indicated in BMBX Rdy bit. be_cmd_fw_initialize too needs to be done before issuing any cmd to FW. be_cmd_fw_initialize is renamed as beiscsi_cmd_special_wrb. Rearrange and rename few functions in init and cleanup path. Signed-off-by: Jitendra Bhivare <jitendra.bhivare@broadcom.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Jitendra Bhivare
committed by
Martin K. Petersen
Martin K. Petersen
parent
480195c267
commit
4d2ee1e688
@@ -21,35 +21,6 @@
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#include "be.h"
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#include "be_mgmt.h"
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int be_chk_reset_complete(struct beiscsi_hba *phba)
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{
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unsigned int num_loop;
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u8 *mpu_sem = 0;
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u32 status;
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num_loop = 1000;
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mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
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msleep(5000);
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while (num_loop) {
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status = readl((void *)mpu_sem);
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if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
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break;
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msleep(60);
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num_loop--;
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}
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if ((status & 0x80000000) || (!num_loop)) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : Failed in be_chk_reset_complete"
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"status = 0x%x\n", status);
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return -EIO;
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}
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return 0;
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}
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struct be_mcc_wrb *alloc_mcc_wrb(struct beiscsi_hba *phba,
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unsigned int *ref_tag)
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{
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@@ -769,87 +740,6 @@ int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
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return status;
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}
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/**
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* be_cmd_fw_initialize()- Initialize FW
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* @ctrl: Pointer to function control structure
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*
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* Send FW initialize pattern for the function.
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*
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* return
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* Success: 0
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* Failure: Non-Zero value
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**/
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int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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int status;
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u8 *endian_check;
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mutex_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x12;
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*endian_check++ = 0x34;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x56;
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*endian_check++ = 0x78;
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*endian_check++ = 0xFF;
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : be_cmd_fw_initialize Failed\n");
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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/**
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* be_cmd_fw_uninit()- Uinitialize FW
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* @ctrl: Pointer to function control structure
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*
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* Send FW uninitialize pattern for the function
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*
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* return
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* Success: 0
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* Failure: Non-Zero value
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**/
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int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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int status;
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u8 *endian_check;
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mutex_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xAA;
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*endian_check++ = 0xBB;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xCC;
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*endian_check++ = 0xDD;
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*endian_check = 0xFF;
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : be_cmd_fw_uninit Failed\n");
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
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struct be_queue_info *cq, struct be_queue_info *eq,
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bool sol_evts, bool no_delay, int coalesce_wm)
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@@ -1293,25 +1183,6 @@ error:
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return status;
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}
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int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
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{
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struct be_ctrl_info *ctrl = &phba->ctrl;
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_post_sgl_pages_req *req = embedded_payload(wrb);
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int status;
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mutex_lock(&ctrl->mbox_lock);
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req = embedded_payload(wrb);
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
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status = be_mbox_notify(ctrl);
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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/**
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* be_cmd_set_vlan()- Configure VLAN paramters on the adapter
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* @phba: device priv structure instance
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@@ -1653,3 +1524,124 @@ int beiscsi_set_uer_feature(struct beiscsi_hba *phba)
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mutex_unlock(&ctrl->mbox_lock);
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return ret;
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}
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static u32 beiscsi_get_post_stage(struct beiscsi_hba *phba)
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{
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u32 sem;
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if (is_chip_be2_be3r(phba))
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sem = ioread32(phba->csr_va + SLIPORT_SEMAPHORE_OFFSET_BEx);
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else
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pci_read_config_dword(phba->pcidev,
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SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
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return sem;
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}
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int beiscsi_check_fw_rdy(struct beiscsi_hba *phba)
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{
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u32 loop, post, rdy = 0;
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loop = 1000;
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while (loop--) {
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post = beiscsi_get_post_stage(phba);
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if (post & POST_ERROR_BIT)
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break;
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if ((post & POST_STAGE_MASK) == POST_STAGE_ARMFW_RDY) {
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rdy = 1;
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break;
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}
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msleep(60);
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}
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if (!rdy) {
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__beiscsi_log(phba, KERN_ERR,
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"BC_%d : FW not ready 0x%x\n", post);
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}
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return rdy;
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}
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static int beiscsi_cmd_function_reset(struct beiscsi_hba *phba)
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{
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struct be_ctrl_info *ctrl = &phba->ctrl;
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_post_sgl_pages_req *req = embedded_payload(wrb);
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int status;
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mutex_lock(&ctrl->mbox_lock);
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req = embedded_payload(wrb);
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
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status = be_mbox_notify(ctrl);
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_cmd_special_wrb(struct be_ctrl_info *ctrl, u32 load)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
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u8 *endian_check;
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int status;
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mutex_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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endian_check = (u8 *) wrb;
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if (load) {
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/* to start communicating */
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*endian_check++ = 0xFF;
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*endian_check++ = 0x12;
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*endian_check++ = 0x34;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0x56;
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*endian_check++ = 0x78;
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*endian_check++ = 0xFF;
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} else {
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/* to stop communicating */
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*endian_check++ = 0xFF;
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*endian_check++ = 0xAA;
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*endian_check++ = 0xBB;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xFF;
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*endian_check++ = 0xCC;
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*endian_check++ = 0xDD;
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*endian_check = 0xFF;
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}
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be_dws_cpu_to_le(wrb, sizeof(*wrb));
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status = be_mbox_notify(ctrl);
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if (status)
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beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
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"BC_%d : special WRB message failed\n");
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mutex_unlock(&ctrl->mbox_lock);
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return status;
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}
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int beiscsi_init_sliport(struct beiscsi_hba *phba)
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{
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int status;
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/* check POST stage before talking to FW */
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status = beiscsi_check_fw_rdy(phba);
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if (!status)
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return -EIO;
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/*
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* SLI COMMON_FUNCTION_RESET completion is indicated by BMBX RDY bit.
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* It should clean up any stale info in FW for this fn.
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*/
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status = beiscsi_cmd_function_reset(phba);
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if (status) {
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beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
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"BC_%d : SLI Function Reset failed\n");
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return status;
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}
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/* indicate driver is loading */
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return beiscsi_cmd_special_wrb(&phba->ctrl, 1);
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}
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