Add support for the latest 1G/10G Chelsio adapter, T3.
This driver is required by the Chelsio T3 RDMA driver posted by Steve Wise. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Divy Le Ray
committato da
Jeff Garzik
Jeff Garzik
parent
0bf94faf64
commit
4d22de3e6c
231
drivers/net/cxgb3/ael1002.c
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231
drivers/net/cxgb3/ael1002.c
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/*
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* This file is part of the Chelsio T3 Ethernet driver.
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*
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* Copyright (C) 2005-2006 Chelsio Communications. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
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* release for licensing terms and conditions.
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*/
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#include "common.h"
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#include "regs.h"
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enum {
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AEL100X_TX_DISABLE = 9,
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AEL100X_TX_CONFIG1 = 0xc002,
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AEL1002_PWR_DOWN_HI = 0xc011,
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AEL1002_PWR_DOWN_LO = 0xc012,
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AEL1002_XFI_EQL = 0xc015,
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AEL1002_LB_EN = 0xc017,
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LASI_CTRL = 0x9002,
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LASI_STAT = 0x9005
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};
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static void ael100x_txon(struct cphy *phy)
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{
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int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
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msleep(100);
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t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
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msleep(30);
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}
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static int ael1002_power_down(struct cphy *phy, int enable)
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{
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int err;
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err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
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if (!err)
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err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_PDOWN, enable ? BMCR_PDOWN : 0);
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return err;
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}
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static int ael1002_reset(struct cphy *phy, int wait)
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{
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int err;
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if ((err = ael1002_power_down(phy, 0)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) ||
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(err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) ||
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(err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN,
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0, 1 << 5)))
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return err;
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return 0;
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}
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static int ael1002_intr_noop(struct cphy *phy)
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{
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return 0;
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}
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static int ael100x_get_link_status(struct cphy *phy, int *link_ok,
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int *speed, int *duplex, int *fc)
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{
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if (link_ok) {
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unsigned int status;
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int err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &status);
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/*
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* BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
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* once more to get the current link state.
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*/
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if (!err && !(status & BMSR_LSTATUS))
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR,
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&status);
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if (err)
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return err;
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*link_ok = !!(status & BMSR_LSTATUS);
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}
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if (speed)
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*speed = SPEED_10000;
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if (duplex)
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*duplex = DUPLEX_FULL;
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return 0;
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}
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static struct cphy_ops ael1002_ops = {
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.reset = ael1002_reset,
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.intr_enable = ael1002_intr_noop,
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.intr_disable = ael1002_intr_noop,
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.intr_clear = ael1002_intr_noop,
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.intr_handler = ael1002_intr_noop,
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.get_link_status = ael100x_get_link_status,
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.power_down = ael1002_power_down,
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};
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void t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops);
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ael100x_txon(phy);
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}
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static int ael1006_reset(struct cphy *phy, int wait)
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{
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return t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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}
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static int ael1006_intr_enable(struct cphy *phy)
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{
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return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1);
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}
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static int ael1006_intr_disable(struct cphy *phy)
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{
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return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0);
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}
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static int ael1006_intr_clear(struct cphy *phy)
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{
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u32 val;
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return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val);
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}
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static int ael1006_intr_handler(struct cphy *phy)
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{
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unsigned int status;
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int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status);
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if (err)
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return err;
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return (status & 1) ? cphy_cause_link_change : 0;
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}
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static int ael1006_power_down(struct cphy *phy, int enable)
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{
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return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_PDOWN, enable ? BMCR_PDOWN : 0);
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}
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static struct cphy_ops ael1006_ops = {
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.reset = ael1006_reset,
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.intr_enable = ael1006_intr_enable,
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.intr_disable = ael1006_intr_disable,
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.intr_clear = ael1006_intr_clear,
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.intr_handler = ael1006_intr_handler,
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.get_link_status = ael100x_get_link_status,
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.power_down = ael1006_power_down,
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};
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void t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops);
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ael100x_txon(phy);
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}
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static struct cphy_ops qt2045_ops = {
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.reset = ael1006_reset,
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.intr_enable = ael1006_intr_enable,
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.intr_disable = ael1006_intr_disable,
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.intr_clear = ael1006_intr_clear,
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.intr_handler = ael1006_intr_handler,
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.get_link_status = ael100x_get_link_status,
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.power_down = ael1006_power_down,
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};
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void t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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unsigned int stat;
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cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops);
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/*
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* Some cards where the PHY is supposed to be at address 0 actually
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* have it at 1.
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*/
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if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) &&
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stat == 0xffff)
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phy->addr = 1;
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}
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static int xaui_direct_reset(struct cphy *phy, int wait)
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{
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return 0;
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}
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static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
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int *speed, int *duplex, int *fc)
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{
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if (link_ok) {
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unsigned int status;
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status = t3_read_reg(phy->adapter,
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XGM_REG(A_XGM_SERDES_STAT0, phy->addr));
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*link_ok = !(status & F_LOWSIG0);
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}
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if (speed)
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*speed = SPEED_10000;
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if (duplex)
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*duplex = DUPLEX_FULL;
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return 0;
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}
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static int xaui_direct_power_down(struct cphy *phy, int enable)
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{
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return 0;
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}
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static struct cphy_ops xaui_direct_ops = {
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.reset = xaui_direct_reset,
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.intr_enable = ael1002_intr_noop,
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.intr_disable = ael1002_intr_noop,
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.intr_clear = ael1002_intr_noop,
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.intr_handler = ael1002_intr_noop,
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.get_link_status = xaui_direct_get_link_status,
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.power_down = xaui_direct_power_down,
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};
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void t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
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int phy_addr, const struct mdio_ops *mdio_ops)
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{
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cphy_init(phy, adapter, 1, &xaui_direct_ops, mdio_ops);
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}
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