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drm/radeon: work around a hw bug in MGCG on CIK

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Always need to set bit 0 of RLC_CGTT_MGCG_OVERRIDE
to avoid unreliable doorbell updates in some cases.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Alex Deucher
2014-11-17 15:08:17 -05:00
parent 3feba08d79
commit 4bb62c95a7
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/radeon/cik.c
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@@ -6344,6 +6344,7 @@ static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
} }
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
data |= 0x00000001;
data &= 0xfffffffd; data &= 0xfffffffd;
if (orig != data) if (orig != data)
WREG32(RLC_CGTT_MGCG_OVERRIDE, data); WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
@@ -6377,7 +6378,7 @@ static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
} }
} else { } else {
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
data |= 0x00000002; data |= 0x00000003;
if (orig != data) if (orig != data)
WREG32(RLC_CGTT_MGCG_OVERRIDE, data); WREG32(RLC_CGTT_MGCG_OVERRIDE, data);