xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain

Browse Source 
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
2015-02-02 23:24:05 +09:00
committed by Sylwester Nawrocki
parent 5785d6e61f
commit 4b8013554b
2 changed files with 394 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

94
include/dt-bindings/clock/exynos5433.h
View File

@@ -110,6 +110,10 @@
#define CLK_DIV_ACLK_G3D_400 137
#define CLK_DIV_ACLK_BUS0_400 138
#define CLK_DIV_ACLK_BUS1_400 139
#define CLK_DIV_SCLK_PCIE_100 140
#define CLK_DIV_SCLK_USBHOST30 141
#define CLK_DIV_SCLK_UFSUNIPRO 142
#define CLK_DIV_SCLK_USBDRD30 143
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -139,8 +143,12 @@
#define CLK_ACLK_BUS1_400 225
#define CLK_ACLK_IMEM_200 226
#define CLK_ACLK_IMEM_266 227
#define CLK_SCLK_PCIE_100_FSYS 228
#define CLK_SCLK_UFSUNIPRO_FSYS 229
#define CLK_SCLK_USBHOST30_FSYS 230
#define CLK_SCLK_USBDRD30_FSYS 231
#define TOP_NR_CLK 228
#define TOP_NR_CLK 232
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -473,6 +481,39 @@
#define CLK_MOUT_SCLK_MMC2_USER 2
#define CLK_MOUT_SCLK_MMC1_USER 3
#define CLK_MOUT_SCLK_MMC0_USER 4
#define CLK_MOUT_SCLK_UFS_MPHY_USER 5
#define CLK_MOUT_SCLK_PCIE_100_USER 6
#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
#define CLK_MOUT_SCLK_USBHOST30_USER 8
#define CLK_MOUT_SCLK_USBDRD30_USER 9
#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
#define CLK_MOUT_SCLK_MPHY 23
#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26
#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27
#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28
#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29
#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31
#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33
#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34
#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37
#define CLK_ACLK_PCIE 50
#define CLK_ACLK_PDMA1 51
@@ -490,8 +531,57 @@
#define CLK_SCLK_MMC0 63
#define CLK_PDMA1 64
#define CLK_PDMA0 65
#define CLK_ACLK_XIU_FSYSPX 66
#define CLK_ACLK_AHB_USBLINKH1 67
#define CLK_ACLK_SMMU_PDMA1 68
#define CLK_ACLK_BTS_PCIE 69
#define CLK_ACLK_AXIUS_PDMA1 70
#define CLK_ACLK_SMMU_PDMA0 71
#define CLK_ACLK_BTS_UFS 72
#define CLK_ACLK_BTS_USBHOST30 73
#define CLK_ACLK_BTS_USBDRD30 74
#define CLK_ACLK_AXIUS_PDMA0 75
#define CLK_ACLK_AXIUS_USBHS 76
#define CLK_ACLK_AXIUS_FSYSSX 77
#define CLK_ACLK_AHB2APB_FSYSP 78
#define CLK_ACLK_AHB2AXI_USBHS 79
#define CLK_ACLK_AHB_USBLINKH0 80
#define CLK_ACLK_AHB_USBHS 81
#define CLK_ACLK_AHB_FSYSH 82
#define CLK_ACLK_XIU_FSYSX 83
#define CLK_ACLK_XIU_FSYSSX 84
#define CLK_ACLK_FSYSNP_200 85
#define CLK_ACLK_FSYSND_200 86
#define CLK_PCLK_PCIE_CTRL 87
#define CLK_PCLK_SMMU_PDMA1 88
#define CLK_PCLK_PCIE_PHY 89
#define CLK_PCLK_BTS_PCIE 90
#define CLK_PCLK_SMMU_PDMA0 91
#define CLK_PCLK_BTS_UFS 92
#define CLK_PCLK_BTS_USBHOST30 93
#define CLK_PCLK_BTS_USBDRD30 94
#define CLK_PCLK_GPIO_FSYS 95
#define CLK_PCLK_PMU_FSYS 96
#define CLK_PCLK_SYSREG_FSYS 97
#define CLK_SCLK_PCIE_100 98
#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
#define CLK_PHYCLK_UFS_RX1_SYMBOL 101
#define CLK_PHYCLK_UFS_RX0_SYMBOL 102
#define CLK_PHYCLK_UFS_TX1_SYMBOL 103
#define CLK_PHYCLK_UFS_TX0_SYMBOL 104
#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
#define CLK_SCLK_MPHY 111
#define CLK_SCLK_UFSUNIPRO 112
#define CLK_SCLK_USBHOST30 113
#define CLK_SCLK_USBDRD30 114
#define FSYS_NR_CLK 66
#define FSYS_NR_CLK 115
/* CMU_G2D */
#define CLK_MUX_ACLK_G2D_266_USER 1