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Merge tag 'mfd-3.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6

Browse Source 
Pull MFD changes from Samuel Ortiz:
 "Besides the usual cleanups, this one brings:

   * Support for 5 new chipsets: Intel's ICH LPC and SCH Centerton,
     ST-E's STAX211, Samsung's MAX77693 and TI's LM3533.

   * Device tree support for the twl6040, tps65910, da9502 and ab8500
     drivers.

   * Fairly big tps56910, ab8500 and db8500 updates.

   * i2c support for mc13xxx.

   * Our regular update for the wm8xxx driver from Mark."

Fix up various conflicts with other trees, largely due to ab5500 removal
etc.

* tag 'mfd-3.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (106 commits)
  mfd: Fix build break of max77693 by adding REGMAP_I2C option
  mfd: Fix twl6040 build failure
  mfd: Fix max77693 build failure
  mfd: ab8500-core should depend on MFD_DB8500_PRCMU
  gpio: tps65910: dt: process gpio specific device node info
  mfd: Remove the parsing of dt info for tps65910 gpio
  mfd: Save device node parsed platform data for tps65910 sub devices
  mfd: Add r_select to lm3533 platform data
  gpio: Add Intel Centerton support to gpio-sch
  mfd: Emulate active low IRQs as well as active high IRQs for wm831x
  mfd: Mark two lm3533 zone registers as volatile
  mfd: Fix return type of lm533 attribute is_visible
  mfd: Enable Device Tree support in the ab8500-pwm driver
  mfd: Enable Device Tree support in the ab8500-sysctrl driver
  mfd: Add support for Device Tree to twl6040
  mfd: Register the twl6040 child for the ASoC codec unconditionally
  mfd: Allocate twl6040 IRQ numbers dynamically
  mfd: twl6040 code cleanup in interrupt initialization part
  mfd: Enable ab8500-gpadc driver for Device Tree
  mfd: Prevent unassigned pointer from being used in ab8500-gpadc driver
  ...
This commit is contained in:
Linus Torvalds
2012-05-29 11:53:11 -07:00
parent 53f2c4a8fd 29f772d41c
commit 4b78147468
94 changed files with 6832 additions and 1783 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
include/linux/mfd/abx500/ab8500.h
View File

@@ -7,6 +7,7 @@
#ifndef MFD_AB8500_H
#define MFD_AB8500_H
#include <linux/atomic.h>
#include <linux/mutex.h>
struct device;
@@ -194,6 +195,14 @@ enum ab8500_version {
#define AB9540_INT_GPIO52F 123
#define AB9540_INT_GPIO53F 124
#define AB9540_INT_GPIO54F 125 /* not 8505 */
/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
#define AB8505_INT_KEYSTUCK 128
#define AB8505_INT_IKR 129
#define AB8505_INT_IKP 130
#define AB8505_INT_KP 131
#define AB8505_INT_KEYDEGLITCH 132
#define AB8505_INT_MODPWRSTATUSF 134
#define AB8505_INT_MODPWRSTATUSR 135
/*
* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
@@ -203,8 +212,8 @@ enum ab8500_version {
* which is larger.
*/
#define AB8500_NR_IRQS 112
#define AB8505_NR_IRQS 128
#define AB9540_NR_IRQS 128
#define AB8505_NR_IRQS 136
#define AB9540_NR_IRQS 136
/* This is set to the roof of any AB8500 chip variant IRQ counts */
#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
@@ -216,6 +225,7 @@ enum ab8500_version {
* @dev: parent device
* @lock: read/write operations lock
* @irq_lock: genirq bus lock
* @transfer_ongoing: 0 if no transfer ongoing
* @irq: irq line
* @version: chip version id (e.g. ab8500 or ab9540)
* @chip_id: chip revision id
@@ -234,7 +244,7 @@ struct ab8500 {
struct device *dev;
struct mutex lock;
struct mutex irq_lock;
atomic_t transfer_ongoing;
int irq_base;
int irq;
enum ab8500_version version;
@@ -280,6 +290,8 @@ extern int __devinit ab8500_init(struct ab8500 *ab8500,
enum ab8500_version version);
extern int __devexit ab8500_exit(struct ab8500 *ab8500);
extern int ab8500_suspend(struct ab8500 *ab8500);
static inline int is_ab8500(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8500;

4
include/linux/mfd/anatop.h
View File

@@ -34,7 +34,7 @@ struct anatop {
spinlock_t reglock;
};
extern u32 anatop_get_bits(struct anatop *, u32, int, int);
extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
extern u32 anatop_read_reg(struct anatop *, u32);
extern void anatop_write_reg(struct anatop *, u32, u32, u32);
#endif /* __LINUX_MFD_ANATOP_H */

2
include/linux/mfd/asic3.h
View File

@@ -31,6 +31,8 @@ struct asic3_platform_data {
unsigned int gpio_base;
unsigned int clock_rate;
struct asic3_led *leds;
};

19
include/linux/mfd/da9052/da9052.h
View File

@@ -33,6 +33,18 @@
#include <linux/mfd/da9052/reg.h>
/* Common - HWMON Channel Definations */
#define DA9052_ADC_VDDOUT 0
#define DA9052_ADC_ICH 1
#define DA9052_ADC_TBAT 2
#define DA9052_ADC_VBAT 3
#define DA9052_ADC_IN4 4
#define DA9052_ADC_IN5 5
#define DA9052_ADC_IN6 6
#define DA9052_ADC_TSI 7
#define DA9052_ADC_TJUNC 8
#define DA9052_ADC_VBBAT 9
#define DA9052_IRQ_DCIN 0
#define DA9052_IRQ_VBUS 1
#define DA9052_IRQ_DCINREM 2
@@ -79,6 +91,9 @@ struct da9052 {
struct device *dev;
struct regmap *regmap;
struct mutex auxadc_lock;
struct completion done;
int irq_base;
struct regmap_irq_chip_data *irq_data;
u8 chip_id;
@@ -86,6 +101,10 @@ struct da9052 {
int chip_irq;
};
/* ADC API */
int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel);
int da9052_adc_read_temp(struct da9052 *da9052);
/* Device I/O API */
static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
{

104
include/linux/mfd/lm3533.h Normal file
View File

@@ -0,0 +1,104 @@
/*
* lm3533.h -- LM3533 interface
*
* Copyright (C) 2011-2012 Texas Instruments
*
* Author: Johan Hovold <jhovold@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_LM3533_H
#define __LINUX_MFD_LM3533_H
#define LM3533_ATTR_RO(_name) \
DEVICE_ATTR(_name, S_IRUGO, show_##_name, NULL)
#define LM3533_ATTR_RW(_name) \
DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name)
struct device;
struct regmap;
struct lm3533 {
struct device *dev;
struct regmap *regmap;
int gpio_hwen;
int irq;
unsigned have_als:1;
unsigned have_backlights:1;
unsigned have_leds:1;
};
struct lm3533_ctrlbank {
struct lm3533 *lm3533;
struct device *dev;
int id;
};
struct lm3533_als_platform_data {
unsigned pwm_mode:1; /* PWM input mode (default analog) */
u8 r_select; /* 1 - 127 (ignored in PWM-mode) */
};
struct lm3533_bl_platform_data {
char *name;
u16 max_current; /* 5000 - 29800 uA (800 uA step) */
u8 default_brightness; /* 0 - 255 */
u8 pwm; /* 0 - 0x3f */
};
struct lm3533_led_platform_data {
char *name;
const char *default_trigger;
u16 max_current; /* 5000 - 29800 uA (800 uA step) */
u8 pwm; /* 0 - 0x3f */
};
enum lm3533_boost_freq {
LM3533_BOOST_FREQ_500KHZ,
LM3533_BOOST_FREQ_1000KHZ,
};
enum lm3533_boost_ovp {
LM3533_BOOST_OVP_16V,
LM3533_BOOST_OVP_24V,
LM3533_BOOST_OVP_32V,
LM3533_BOOST_OVP_40V,
};
struct lm3533_platform_data {
int gpio_hwen;
enum lm3533_boost_ovp boost_ovp;
enum lm3533_boost_freq boost_freq;
struct lm3533_als_platform_data *als;
struct lm3533_bl_platform_data *backlights;
int num_backlights;
struct lm3533_led_platform_data *leds;
int num_leds;
};
extern int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb);
extern int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb);
extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val);
extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val);
extern int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb,
u16 imax);
extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val);
extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val);
extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val);
extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val);
extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask);
#endif /* __LINUX_MFD_LM3533_H */

48
include/linux/mfd/lpc_ich.h Normal file
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@@ -0,0 +1,48 @@
/*
* linux/drivers/mfd/lpc_ich.h
*
* Copyright (c) 2012 Extreme Engineering Solution, Inc.
* Author: Aaron Sierra <asierra@xes-inc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License 2 as published
* by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef LPC_ICH_H
#define LPC_ICH_H
/* Watchdog resources */
#define ICH_RES_IO_TCO 0
#define ICH_RES_IO_SMI 1
#define ICH_RES_MEM_OFF 2
#define ICH_RES_MEM_GCS 0
/* GPIO resources */
#define ICH_RES_GPIO 0
#define ICH_RES_GPE0 1
/* GPIO compatibility */
#define ICH_I3100_GPIO 0x401
#define ICH_V5_GPIO 0x501
#define ICH_V6_GPIO 0x601
#define ICH_V7_GPIO 0x701
#define ICH_V9_GPIO 0x801
#define ICH_V10CORP_GPIO 0xa01
#define ICH_V10CONS_GPIO 0xa11
struct lpc_ich_info {
char name[32];
unsigned int iTCO_version;
unsigned int gpio_version;
};
#endif

227
include/linux/mfd/max77693-private.h Normal file
View File

@@ -0,0 +1,227 @@
/*
* max77693-private.h - Voltage regulator driver for the Maxim 77693
*
* Copyright (C) 2012 Samsung Electrnoics
* SangYoung Son <hello.son@samsung.com>
*
* This program is not provided / owned by Maxim Integrated Products.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX77693_PRIV_H
#define __LINUX_MFD_MAX77693_PRIV_H
#include <linux/i2c.h>
#define MAX77693_NUM_IRQ_MUIC_REGS 3
#define MAX77693_REG_INVALID (0xff)
/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
enum max77693_pmic_reg {
MAX77693_LED_REG_IFLASH1 = 0x00,
MAX77693_LED_REG_IFLASH2 = 0x01,
MAX77693_LED_REG_ITORCH = 0x02,
MAX77693_LED_REG_ITORCHTIMER = 0x03,
MAX77693_LED_REG_FLASH_TIMER = 0x04,
MAX77693_LED_REG_FLASH_EN = 0x05,
MAX77693_LED_REG_MAX_FLASH1 = 0x06,
MAX77693_LED_REG_MAX_FLASH2 = 0x07,
MAX77693_LED_REG_MAX_FLASH3 = 0x08,
MAX77693_LED_REG_MAX_FLASH4 = 0x09,
MAX77693_LED_REG_VOUT_CNTL = 0x0A,
MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
MAX77693_LED_REG_FLASH_INT = 0x0E,
MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
MAX77693_LED_REG_FLASH_INT_STATUS = 0x10,
MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
MAX77693_PMIC_REG_INTSRC = 0x22,
MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
MAX77693_PMIC_REG_LSCNFG = 0x2B,
MAX77693_CHG_REG_CHG_INT = 0xB0,
MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
MAX77693_PMIC_REG_END,
};
/* Slave addr = 0x4A: MUIC */
enum max77693_muic_reg {
MAX77693_MUIC_REG_ID = 0x00,
MAX77693_MUIC_REG_INT1 = 0x01,
MAX77693_MUIC_REG_INT2 = 0x02,
MAX77693_MUIC_REG_INT3 = 0x03,
MAX77693_MUIC_REG_STATUS1 = 0x04,
MAX77693_MUIC_REG_STATUS2 = 0x05,
MAX77693_MUIC_REG_STATUS3 = 0x06,
MAX77693_MUIC_REG_INTMASK1 = 0x07,
MAX77693_MUIC_REG_INTMASK2 = 0x08,
MAX77693_MUIC_REG_INTMASK3 = 0x09,
MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
MAX77693_MUIC_REG_CTRL1 = 0x0C,
MAX77693_MUIC_REG_CTRL2 = 0x0D,
MAX77693_MUIC_REG_CTRL3 = 0x0E,
MAX77693_MUIC_REG_END,
};
/* Slave addr = 0x90: Haptic */
enum max77693_haptic_reg {
MAX77693_HAPTIC_REG_STATUS = 0x00,
MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
MAX77693_HAPTIC_REG_REV = 0x10,
MAX77693_HAPTIC_REG_END,
};
enum max77693_irq_source {
LED_INT = 0,
TOPSYS_INT,
CHG_INT,
MUIC_INT1,
MUIC_INT2,
MUIC_INT3,
MAX77693_IRQ_GROUP_NR,
};
enum max77693_irq {
/* PMIC - FLASH */
MAX77693_LED_IRQ_FLED2_OPEN,
MAX77693_LED_IRQ_FLED2_SHORT,
MAX77693_LED_IRQ_FLED1_OPEN,
MAX77693_LED_IRQ_FLED1_SHORT,
MAX77693_LED_IRQ_MAX_FLASH,
/* PMIC - TOPSYS */
MAX77693_TOPSYS_IRQ_T120C_INT,
MAX77693_TOPSYS_IRQ_T140C_INT,
MAX77693_TOPSYS_IRQ_LOWSYS_INT,
/* PMIC - Charger */
MAX77693_CHG_IRQ_BYP_I,
MAX77693_CHG_IRQ_THM_I,
MAX77693_CHG_IRQ_BAT_I,
MAX77693_CHG_IRQ_CHG_I,
MAX77693_CHG_IRQ_CHGIN_I,
/* MUIC INT1 */
MAX77693_MUIC_IRQ_INT1_ADC,
MAX77693_MUIC_IRQ_INT1_ADC_LOW,
MAX77693_MUIC_IRQ_INT1_ADC_ERR,
MAX77693_MUIC_IRQ_INT1_ADC1K,
/* MUIC INT2 */
MAX77693_MUIC_IRQ_INT2_CHGTYP,
MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
MAX77693_MUIC_IRQ_INT2_DCDTMR,
MAX77693_MUIC_IRQ_INT2_DXOVP,
MAX77693_MUIC_IRQ_INT2_VBVOLT,
MAX77693_MUIC_IRQ_INT2_VIDRM,
/* MUIC INT3 */
MAX77693_MUIC_IRQ_INT3_EOC,
MAX77693_MUIC_IRQ_INT3_CGMBC,
MAX77693_MUIC_IRQ_INT3_OVP,
MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
MAX77693_MUIC_IRQ_INT3_BAT_DET,
MAX77693_IRQ_NR,
};
struct max77693_dev {
struct device *dev;
struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */
struct i2c_client *muic; /* 0x4A , MUIC */
struct i2c_client *haptic; /* 0x90 , Haptic */
struct mutex iolock;
int type;
struct regmap *regmap;
struct regmap *regmap_muic;
struct regmap *regmap_haptic;
struct irq_domain *irq_domain;
int irq;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
};
enum max77693_types {
TYPE_MAX77693,
};
extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
u8 *buf);
extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
u8 *buf);
extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
extern int max77693_irq_init(struct max77693_dev *max77686);
extern void max77693_irq_exit(struct max77693_dev *max77686);
extern int max77693_irq_resume(struct max77693_dev *max77686);
#endif /* __LINUX_MFD_MAX77693_PRIV_H */

36
include/linux/mfd/max77693.h Normal file
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@@ -0,0 +1,36 @@
/*
* max77693.h - Driver for the Maxim 77693
*
* Copyright (C) 2012 Samsung Electrnoics
* SangYoung Son <hello.son@samsung.com>
*
* This program is not provided / owned by Maxim Integrated Products.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max8997.h
*
* MAX77693 has PMIC, Charger, Flash LED, Haptic, MUIC devices.
* The devices share the same I2C bus and included in
* this mfd driver.
*/
#ifndef __LINUX_MFD_MAX77693_H
#define __LINUX_MFD_MAX77693_H
struct max77693_platform_data {
int wakeup;
};
#endif /* __LINUX_MFD_MAX77693_H */

324
include/linux/mfd/sta2x11-mfd.h Normal file
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@@ -0,0 +1,324 @@
/*
* Copyright (c) 2009-2011 Wind River Systems, Inc.
* Copyright (c) 2011 ST Microelectronics (Alessandro Rubini)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* The STMicroelectronics ConneXt (STA2X11) chip has several unrelated
* functions in one PCI endpoint functions. This driver simply
* registers the platform devices in this iomemregion and exports a few
* functions to access common registers
*/
#ifndef __STA2X11_MFD_H
#define __STA2X11_MFD_H
#include <linux/types.h>
#include <linux/pci.h>
/*
* The MFD PCI block includes the GPIO peripherals and other register blocks.
* For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
*/
#define GSTA_GPIO_PER_BLOCK 32
#define GSTA_NR_BLOCKS 4
#define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS)
/* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */
struct sta2x11_gpio_pdata {
unsigned pinconfig[GSTA_NR_GPIO];
};
/* Macros below lifted from sh_pfc.h, with minor differences */
#define PINMUX_TYPE_NONE 0
#define PINMUX_TYPE_FUNCTION 1
#define PINMUX_TYPE_OUTPUT_LOW 2
#define PINMUX_TYPE_OUTPUT_HIGH 3
#define PINMUX_TYPE_INPUT 4
#define PINMUX_TYPE_INPUT_PULLUP 5
#define PINMUX_TYPE_INPUT_PULLDOWN 6
/* Give names to GPIO pins, like PXA does, taken from the manual */
#define STA2X11_GPIO0 0
#define STA2X11_GPIO1 1
#define STA2X11_GPIO2 2
#define STA2X11_GPIO3 3
#define STA2X11_GPIO4 4
#define STA2X11_GPIO5 5
#define STA2X11_GPIO6 6
#define STA2X11_GPIO7 7
#define STA2X11_GPIO8_RGBOUT_RED7 8
#define STA2X11_GPIO9_RGBOUT_RED6 9
#define STA2X11_GPIO10_RGBOUT_RED5 10
#define STA2X11_GPIO11_RGBOUT_RED4 11
#define STA2X11_GPIO12_RGBOUT_RED3 12
#define STA2X11_GPIO13_RGBOUT_RED2 13
#define STA2X11_GPIO14_RGBOUT_RED1 14
#define STA2X11_GPIO15_RGBOUT_RED0 15
#define STA2X11_GPIO16_RGBOUT_GREEN7 16
#define STA2X11_GPIO17_RGBOUT_GREEN6 17
#define STA2X11_GPIO18_RGBOUT_GREEN5 18
#define STA2X11_GPIO19_RGBOUT_GREEN4 19
#define STA2X11_GPIO20_RGBOUT_GREEN3 20
#define STA2X11_GPIO21_RGBOUT_GREEN2 21
#define STA2X11_GPIO22_RGBOUT_GREEN1 22
#define STA2X11_GPIO23_RGBOUT_GREEN0 23
#define STA2X11_GPIO24_RGBOUT_BLUE7 24
#define STA2X11_GPIO25_RGBOUT_BLUE6 25
#define STA2X11_GPIO26_RGBOUT_BLUE5 26
#define STA2X11_GPIO27_RGBOUT_BLUE4 27
#define STA2X11_GPIO28_RGBOUT_BLUE3 28
#define STA2X11_GPIO29_RGBOUT_BLUE2 29
#define STA2X11_GPIO30_RGBOUT_BLUE1 30
#define STA2X11_GPIO31_RGBOUT_BLUE0 31
#define STA2X11_GPIO32_RGBOUT_VSYNCH 32
#define STA2X11_GPIO33_RGBOUT_HSYNCH 33
#define STA2X11_GPIO34_RGBOUT_DEN 34
#define STA2X11_GPIO35_ETH_CRS_DV 35
#define STA2X11_GPIO36_ETH_TXD1 36
#define STA2X11_GPIO37_ETH_TXD0 37
#define STA2X11_GPIO38_ETH_TX_EN 38
#define STA2X11_GPIO39_MDIO 39
#define STA2X11_GPIO40_ETH_REF_CLK 40
#define STA2X11_GPIO41_ETH_RXD1 41
#define STA2X11_GPIO42_ETH_RXD0 42
#define STA2X11_GPIO43_MDC 43
#define STA2X11_GPIO44_CAN_TX 44
#define STA2X11_GPIO45_CAN_RX 45
#define STA2X11_GPIO46_MLB_DAT 46
#define STA2X11_GPIO47_MLB_SIG 47
#define STA2X11_GPIO48_SPI0_CLK 48
#define STA2X11_GPIO49_SPI0_TXD 49
#define STA2X11_GPIO50_SPI0_RXD 50
#define STA2X11_GPIO51_SPI0_FRM 51
#define STA2X11_GPIO52_SPI1_CLK 52
#define STA2X11_GPIO53_SPI1_TXD 53
#define STA2X11_GPIO54_SPI1_RXD 54
#define STA2X11_GPIO55_SPI1_FRM 55
#define STA2X11_GPIO56_SPI2_CLK 56
#define STA2X11_GPIO57_SPI2_TXD 57
#define STA2X11_GPIO58_SPI2_RXD 58
#define STA2X11_GPIO59_SPI2_FRM 59
#define STA2X11_GPIO60_I2C0_SCL 60
#define STA2X11_GPIO61_I2C0_SDA 61
#define STA2X11_GPIO62_I2C1_SCL 62
#define STA2X11_GPIO63_I2C1_SDA 63
#define STA2X11_GPIO64_I2C2_SCL 64
#define STA2X11_GPIO65_I2C2_SDA 65
#define STA2X11_GPIO66_I2C3_SCL 66
#define STA2X11_GPIO67_I2C3_SDA 67
#define STA2X11_GPIO68_MSP0_RCK 68
#define STA2X11_GPIO69_MSP0_RXD 69
#define STA2X11_GPIO70_MSP0_RFS 70
#define STA2X11_GPIO71_MSP0_TCK 71
#define STA2X11_GPIO72_MSP0_TXD 72
#define STA2X11_GPIO73_MSP0_TFS 73
#define STA2X11_GPIO74_MSP0_SCK 74
#define STA2X11_GPIO75_MSP1_CK 75
#define STA2X11_GPIO76_MSP1_RXD 76
#define STA2X11_GPIO77_MSP1_FS 77
#define STA2X11_GPIO78_MSP1_TXD 78
#define STA2X11_GPIO79_MSP2_CK 79
#define STA2X11_GPIO80_MSP2_RXD 80
#define STA2X11_GPIO81_MSP2_FS 81
#define STA2X11_GPIO82_MSP2_TXD 82
#define STA2X11_GPIO83_MSP3_CK 83
#define STA2X11_GPIO84_MSP3_RXD 84
#define STA2X11_GPIO85_MSP3_FS 85
#define STA2X11_GPIO86_MSP3_TXD 86
#define STA2X11_GPIO87_MSP4_CK 87
#define STA2X11_GPIO88_MSP4_RXD 88
#define STA2X11_GPIO89_MSP4_FS 89
#define STA2X11_GPIO90_MSP4_TXD 90
#define STA2X11_GPIO91_MSP5_CK 91
#define STA2X11_GPIO92_MSP5_RXD 92
#define STA2X11_GPIO93_MSP5_FS 93
#define STA2X11_GPIO94_MSP5_TXD 94
#define STA2X11_GPIO95_SDIO3_DAT3 95
#define STA2X11_GPIO96_SDIO3_DAT2 96
#define STA2X11_GPIO97_SDIO3_DAT1 97
#define STA2X11_GPIO98_SDIO3_DAT0 98
#define STA2X11_GPIO99_SDIO3_CLK 99
#define STA2X11_GPIO100_SDIO3_CMD 100
#define STA2X11_GPIO101 101
#define STA2X11_GPIO102 102
#define STA2X11_GPIO103 103
#define STA2X11_GPIO104 104
#define STA2X11_GPIO105_SDIO2_DAT3 105
#define STA2X11_GPIO106_SDIO2_DAT2 106
#define STA2X11_GPIO107_SDIO2_DAT1 107
#define STA2X11_GPIO108_SDIO2_DAT0 108
#define STA2X11_GPIO109_SDIO2_CLK 109
#define STA2X11_GPIO110_SDIO2_CMD 110
#define STA2X11_GPIO111 111
#define STA2X11_GPIO112 112
#define STA2X11_GPIO113 113
#define STA2X11_GPIO114 114
#define STA2X11_GPIO115_SDIO1_DAT3 115
#define STA2X11_GPIO116_SDIO1_DAT2 116
#define STA2X11_GPIO117_SDIO1_DAT1 117
#define STA2X11_GPIO118_SDIO1_DAT0 118
#define STA2X11_GPIO119_SDIO1_CLK 119
#define STA2X11_GPIO120_SDIO1_CMD 120
#define STA2X11_GPIO121 121
#define STA2X11_GPIO122 122
#define STA2X11_GPIO123 123
#define STA2X11_GPIO124 124
#define STA2X11_GPIO125_UART2_TXD 125
#define STA2X11_GPIO126_UART2_RXD 126
#define STA2X11_GPIO127_UART3_TXD 127
/*
* The APB bridge has its own registers, needed by our users as well.
* They are accessed with the following read/mask/write function.
*/
u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
/* CAN and MLB */
#define APBREG_BSR 0x00 /* Bridge Status Reg */
#define APBREG_PAER 0x08 /* Peripherals Address Error Reg */
#define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
#define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
#define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
#define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
#define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
#define APBREG_CAN (1 << 1)
#define APBREG_MLB (1 << 3)
/* SARAC */
#define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */
#define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */
#define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
#define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
#define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
#define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
#define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
#define APBREG_SARAC (1 << 2)
/*
* The system controller has its own registers. Some of these are accessed
* by out users as well, using the following read/mask/write/function
*/
u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
#define SCTL_SCCTL 0x00 /* System controller control register */
#define SCTL_ARMCFG 0x04 /* ARM configuration register */
#define SCTL_SCPLLCTL 0x08 /* PLL control status register */
#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
#define SCTL_SCGRST 0x28 /* Peripheral global reset */
#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
#define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */
#define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */
#define SCTL_SCINTREN 0x44 /* Interrupt enable */
#define SCTL_SCRISR 0x48 /* RAW interrupt status */
#define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */
#define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */
#define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */
#define SCTL_SCRSTSTA 0x58 /* Reset status register */
#define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0)
#define SCTL_SCRESCTRL1_USB_OTG (1 << 1)
#define SCTL_SCRESCTRL1_USB_HRST (1 << 2)
#define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3)
#define SCTL_SCRESCTRL1_SATAII (1 << 4)
#define SCTL_SCRESCTRL1_VIP (1 << 5)
#define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6)
#define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7)
#define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8)
#define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9)
#define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10)
#define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11)
#define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12)
#define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13)
#define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14)
#define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15)
#define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16)
#define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17)
#define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18)
#define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19)
#define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20)
#define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21)
#define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22)
#define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23)
#define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24)
#define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25)
#define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26)
#define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27)
#define SCTL_SCRESCTRL1_PER_MMC (1 << 28)
#define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29)
#define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30)
#define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31)
#define SCTL_SCPEREN0_UART0 (1 << 0)
#define SCTL_SCPEREN0_UART1 (1 << 1)
#define SCTL_SCPEREN0_UART2 (1 << 2)
#define SCTL_SCPEREN0_UART3 (1 << 3)
#define SCTL_SCPEREN0_MSP0 (1 << 4)
#define SCTL_SCPEREN0_MSP1 (1 << 5)
#define SCTL_SCPEREN0_MSP2 (1 << 6)
#define SCTL_SCPEREN0_MSP3 (1 << 7)
#define SCTL_SCPEREN0_MSP4 (1 << 8)
#define SCTL_SCPEREN0_MSP5 (1 << 9)
#define SCTL_SCPEREN0_SPI0 (1 << 10)
#define SCTL_SCPEREN0_SPI1 (1 << 11)
#define SCTL_SCPEREN0_SPI2 (1 << 12)
#define SCTL_SCPEREN0_I2C0 (1 << 13)
#define SCTL_SCPEREN0_I2C1 (1 << 14)
#define SCTL_SCPEREN0_I2C2 (1 << 15)
#define SCTL_SCPEREN0_I2C3 (1 << 16)
#define SCTL_SCPEREN0_SVDO_LVDS (1 << 17)
#define SCTL_SCPEREN0_USB_HOST (1 << 18)
#define SCTL_SCPEREN0_USB_OTG (1 << 19)
#define SCTL_SCPEREN0_MCI0 (1 << 20)
#define SCTL_SCPEREN0_MCI1 (1 << 21)
#define SCTL_SCPEREN0_MCI2 (1 << 22)
#define SCTL_SCPEREN0_MCI3 (1 << 23)
#define SCTL_SCPEREN0_SATA (1 << 24)
#define SCTL_SCPEREN0_ETHERNET (1 << 25)
#define SCTL_SCPEREN0_VIC (1 << 26)
#define SCTL_SCPEREN0_DMA_AUDIO (1 << 27)
#define SCTL_SCPEREN0_DMA_SOC (1 << 28)
#define SCTL_SCPEREN0_RAM (1 << 29)
#define SCTL_SCPEREN0_VIP (1 << 30)
#define SCTL_SCPEREN0_ARM (1 << 31)
#define SCTL_SCPEREN1_UART0 (1 << 0)
#define SCTL_SCPEREN1_UART1 (1 << 1)
#define SCTL_SCPEREN1_UART2 (1 << 2)
#define SCTL_SCPEREN1_UART3 (1 << 3)
#define SCTL_SCPEREN1_MSP0 (1 << 4)
#define SCTL_SCPEREN1_MSP1 (1 << 5)
#define SCTL_SCPEREN1_MSP2 (1 << 6)
#define SCTL_SCPEREN1_MSP3 (1 << 7)
#define SCTL_SCPEREN1_MSP4 (1 << 8)
#define SCTL_SCPEREN1_MSP5 (1 << 9)
#define SCTL_SCPEREN1_SPI0 (1 << 10)
#define SCTL_SCPEREN1_SPI1 (1 << 11)
#define SCTL_SCPEREN1_SPI2 (1 << 12)
#define SCTL_SCPEREN1_I2C0 (1 << 13)
#define SCTL_SCPEREN1_I2C1 (1 << 14)
#define SCTL_SCPEREN1_I2C2 (1 << 15)
#define SCTL_SCPEREN1_I2C3 (1 << 16)
#define SCTL_SCPEREN1_USB_PHY (1 << 17)
#endif /* __STA2X11_MFD_H */

2
include/linux/mfd/stmpe.h
View File

@@ -117,7 +117,7 @@ struct matrix_keymap_data;
* @no_autorepeat: disable key autorepeat
*/
struct stmpe_keypad_platform_data {
struct matrix_keymap_data *keymap_data;
const struct matrix_keymap_data *keymap_data;
unsigned int debounce_ms;
unsigned int scan_count;
bool no_autorepeat;

49
include/linux/mfd/tps65910.h
View File

@@ -18,6 +18,7 @@
#define __LINUX_MFD_TPS65910_H
#include <linux/gpio.h>
#include <linux/regmap.h>
/* TPS chip id list */
#define TPS65910 0
@@ -783,6 +784,18 @@
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4
#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8
/*
* Sleep keepon data: Maintains the state in sleep mode
* @therm_keepon: Keep on the thermal monitoring in sleep state.
* @clkout32k_keepon: Keep on the 32KHz clock output in sleep state.
* @i2chs_keepon: Keep on high speed internal clock in sleep state.
*/
struct tps65910_sleep_keepon_data {
unsigned therm_keepon:1;
unsigned clkout32k_keepon:1;
unsigned i2chs_keepon:1;
};
/**
* struct tps65910_board
* Board platform data may be used to initialize regulators.
@@ -794,6 +807,8 @@ struct tps65910_board {
int irq_base;
int vmbch_threshold;
int vmbch2_threshold;
bool en_dev_slp;
struct tps65910_sleep_keepon_data *slp_keepon;
bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
@@ -809,16 +824,14 @@ struct tps65910 {
struct regmap *regmap;
struct mutex io_mutex;
unsigned int id;
int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
/* Client devices */
struct tps65910_pmic *pmic;
struct tps65910_rtc *rtc;
struct tps65910_power *power;
/* GPIO Handling */
struct gpio_chip gpio;
/* Device node parsed board data */
struct tps65910_board *of_plat_data;
/* IRQ Handling */
struct mutex irq_lock;
@@ -826,6 +839,7 @@ struct tps65910 {
int irq_base;
int irq_num;
u32 irq_mask;
struct irq_domain *domain;
};
struct tps65910_platform_data {
@@ -833,9 +847,6 @@ struct tps65910_platform_data {
int irq_base;
};
int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
int tps65910_irq_init(struct tps65910 *tps65910, int irq,
struct tps65910_platform_data *pdata);
int tps65910_irq_exit(struct tps65910 *tps65910);
@@ -845,4 +856,28 @@ static inline int tps65910_chip_id(struct tps65910 *tps65910)
return tps65910->id;
}
static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg,
unsigned int *val)
{
return regmap_read(tps65910->regmap, reg, val);
}
static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg,
unsigned int val)
{
return regmap_write(tps65910->regmap, reg, val);
}
static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg,
u8 mask)
{
return regmap_update_bits(tps65910->regmap, reg, mask, mask);
}
static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg,
u8 mask)
{
return regmap_update_bits(tps65910->regmap, reg, mask, 0);
}
#endif /* __LINUX_MFD_TPS65910_H */

2
include/linux/mfd/twl6040.h
View File

@@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/regulator/consumer.h>
#define TWL6040_REG_ASICID 0x01
#define TWL6040_REG_ASICREV 0x02
@@ -203,6 +204,7 @@ struct regmap;
struct twl6040 {
struct device *dev;
struct regmap *regmap;
struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
struct mutex mutex;
struct mutex io_mutex;
struct mutex irq_mutex;

12
include/linux/mfd/wm831x/core.h
View File

@@ -17,6 +17,7 @@
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/list.h>
#include <linux/regmap.h>
@@ -338,6 +339,7 @@
#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
struct regulator_dev;
struct irq_domain;
#define WM831X_NUM_IRQ_REGS 5
#define WM831X_NUM_GPIO_REGS 16
@@ -367,7 +369,7 @@ struct wm831x {
int irq; /* Our chip IRQ */
struct mutex irq_lock;
int irq_base;
struct irq_domain *irq_domain;
int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
@@ -382,7 +384,8 @@ struct wm831x {
/* Used by the interrupt controller code to post writes */
int gpio_update[WM831X_NUM_GPIO_REGS];
bool gpio_level[WM831X_NUM_GPIO_REGS];
bool gpio_level_high[WM831X_NUM_GPIO_REGS];
bool gpio_level_low[WM831X_NUM_GPIO_REGS];
struct mutex auxadc_lock;
struct list_head auxadc_pending;
@@ -417,6 +420,11 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq);
void wm831x_irq_exit(struct wm831x *wm831x);
void wm831x_auxadc_init(struct wm831x *wm831x);
static inline int wm831x_irq(struct wm831x *wm831x, int irq)
{
return irq_create_mapping(wm831x->irq_domain, irq);
}
extern struct regmap_config wm831x_regmap_config;
#endif

9
include/linux/mfd/wm8350/core.h
View File

@@ -602,6 +602,7 @@ extern const u16 wm8352_mode2_defaults[];
extern const u16 wm8352_mode3_defaults[];
struct wm8350;
struct regmap;
struct wm8350_hwmon {
struct platform_device *pdev;
@@ -612,13 +613,7 @@ struct wm8350 {
struct device *dev;
/* device IO */
union {
struct i2c_client *i2c_client;
struct spi_device *spi_device;
};
int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
void *src);
struct regmap *regmap;
u16 *reg_cache;
struct mutex auxadc_mutex;

14
include/linux/mfd/wm8400-private.h
View File

@@ -24,19 +24,14 @@
#include <linux/mfd/wm8400.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
struct regmap;
#include <linux/regmap.h>
#define WM8400_REGISTER_COUNT 0x55
struct wm8400 {
struct device *dev;
struct mutex io_lock;
struct regmap *regmap;
u16 reg_cache[WM8400_REGISTER_COUNT];
struct platform_device regulators[6];
};
@@ -930,6 +925,11 @@ struct wm8400 {
u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
static inline int wm8400_set_bits(struct wm8400 *wm8400, u8 reg,
u16 mask, u16 val)
{
return regmap_update_bits(wm8400->regmap, reg, mask, val);
}
#endif

1
include/linux/mfd/wm8994/core.h
View File

@@ -57,6 +57,7 @@ struct wm8994 {
enum wm8994_type type;
int revision;
int cust_id;
struct device *dev;
struct regmap *regmap;

3
include/linux/mfd/wm8994/registers.h
View File

@@ -2212,6 +2212,9 @@
/*
* R256 (0x100) - Chip Revision
*/
#define WM8994_CUST_ID_MASK 0xFF00 /* CUST_ID - [15:8] */
#define WM8994_CUST_ID_SHIFT 8 /* CUST_ID - [15:8] */
#define WM8994_CUST_ID_WIDTH 8 /* CUST_ID - [15:8] */
#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */