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Merge tag 'stm32-dt-for-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt

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Pull "STM32 DT updates for v4.11, round 2" from Alexandre Torgue:

Highlights:
----------

 - ADD Timers support on STM32F429 MCU
 - Enable PWM1 & PWM3 on STM32F469 Disco board
 - Fix STM32F4_X_CLOCK macro
 - Use STM32F4_X_CLOCK macro in STM32 device tree
 - Add I2C1 support for STM32F429 MCU
 - Enable I2C1 on STM32F429 eval board

* tag 'stm32-dt-for-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: Add I2C1 support for STM32429 eval board
  ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
  ARM: dts: stm32: Use clock DT binding definition on stm32f429 family
  dt-bindings: mfd: stm32f4: Add missing binding definition
  dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro
  ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
  ARM: dts: stm32: add Timers driver for stm32f429 MCU
This commit is contained in:
Arnd Bergmann
2017-02-07 15:25:19 +01:00
parent 54fe90874f 390891d0ba
commit 4b5f4835d1
4 changed files with 388 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
include/dt-bindings/mfd/stm32f4-rcc.h
View File

@@ -18,14 +18,20 @@
#define STM32F4_RCC_AHB1_GPIOJ 9
#define STM32F4_RCC_AHB1_GPIOK 10
#define STM32F4_RCC_AHB1_CRC 12
#define STM32F4_RCC_AHB1_BKPSRAM 18
#define STM32F4_RCC_AHB1_CCMDATARAM 20
#define STM32F4_RCC_AHB1_DMA1 21
#define STM32F4_RCC_AHB1_DMA2 22
#define STM32F4_RCC_AHB1_DMA2D 23
#define STM32F4_RCC_AHB1_ETHMAC 25
#define STM32F4_RCC_AHB1_OTGHS 29
#define STM32F4_RCC_AHB1_ETHMACTX 26
#define STM32F4_RCC_AHB1_ETHMACRX 27
#define STM32F4_RCC_AHB1_ETHMACPTP 28
#define STM32F4_RCC_AHB1_OTGHS 29
#define STM32F4_RCC_AHB1_OTGHSULPI 30
#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit + (0x30 * 8))
#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
/* AHB2 */
@@ -36,13 +42,14 @@
#define STM32F4_RCC_AHB2_OTGFS 7
#define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + (0x34 * 8))
#define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
/* AHB3 */
#define STM32F4_RCC_AHB3_FMC 0
#define STM32F4_RCC_AHB3_QSPI 1
#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8))
#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + (0x38 * 8))
#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40)
/* APB1 */
#define STM32F4_RCC_APB1_TIM2 0
@@ -72,14 +79,16 @@
#define STM32F4_RCC_APB1_UART8 31
#define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8))
#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + (0x40 * 8))
#define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80)
/* APB2 */
#define STM32F4_RCC_APB2_TIM1 0
#define STM32F4_RCC_APB2_TIM8 1
#define STM32F4_RCC_APB2_USART1 4
#define STM32F4_RCC_APB2_USART6 5
#define STM32F4_RCC_APB2_ADC 8
#define STM32F4_RCC_APB2_ADC1 8
#define STM32F4_RCC_APB2_ADC2 9
#define STM32F4_RCC_APB2_ADC3 10
#define STM32F4_RCC_APB2_SDIO 11
#define STM32F4_RCC_APB2_SPI1 12
#define STM32F4_RCC_APB2_SPI4 13
@@ -91,8 +100,9 @@
#define STM32F4_RCC_APB2_SPI6 21
#define STM32F4_RCC_APB2_SAI1 22
#define STM32F4_RCC_APB2_LTDC 26
#define STM32F4_RCC_APB2_DSI 27
#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + (0x44 * 8))
#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0)
#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */