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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC platform support updates from Kevin Hilman:
 "Our SoC branch usually contains expanded support for new SoCs and
  other core platform code.  Some highlights from this round:

   - sunxi: SMP support for A23 SoC
   - socpga: big-endian support
   - pxa: conversion to common clock framework
   - bcm: SMP support for BCM63138
   - imx: support new I.MX7D SoC
   - zte: basic support for ZX296702 SoC"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
  ARM: zx: Add basic defconfig support for ZX296702
  ARM: dts: zx: add an initial zx296702 dts and doc
  clk: zx: add clock support to zx296702
  dt-bindings: Add #defines for ZTE ZX296702 clocks
  ARM: socfpga: fix build error due to secondary_startup
  MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
  ARM: ep93xx: simone: support for SPI-based MMC/SD cards
  MAINTAINERS: update Shawn's email to use kernel.org one
  ARM: socfpga: support suspend to ram
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
  ARM: EXYNOS: register power domain driver from core_initcall
  ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
  ARM: SAMSUNG: Constify platform_device_id
  ARM: EXYNOS: Constify irq_domain_ops
  ARM: EXYNOS: add coupled cpuidle support for Exynos3250
  ARM: EXYNOS: add exynos_get_boot_addr() helper
  ARM: EXYNOS: add exynos_set_boot_addr() helper
  ARM: EXYNOS: make exynos_core_restart() less verbose
  ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
  ...
This commit is contained in:
Linus Torvalds
2015-06-26 11:34:35 -07:00
parent c11d716218 2879e43f09
commit 4aa705b18b
217 changed files with 6574 additions and 2063 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-omap1/ams-delta-fiq-handler.S
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@@ -17,11 +17,10 @@
#include <asm/assembler.h>
#include <mach/board-ams-delta.h>
#include <mach/irqs.h>
#include <mach/ams-delta-fiq.h>
#include "iomap.h"
#include "soc.h"
/*
* GPIO related definitions, copied from arch/arm/plat-omap/gpio.c.

1
arch/arm/mach-omap1/board-ams-delta.c
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@@ -626,6 +626,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
.map_io = ams_delta_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = ams_delta_init,
.init_late = ams_delta_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-fsample.c
View File

@@ -362,6 +362,7 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
.map_io = omap_fsample_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_fsample_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-generic.c
View File

@@ -82,6 +82,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
.map_io = omap16xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_generic_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-h2.c
View File

@@ -426,6 +426,7 @@ MACHINE_START(OMAP_H2, "TI-H2")
.map_io = omap16xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = h2_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-h3-mmc.c
View File

@@ -16,6 +16,7 @@
#include <linux/i2c/tps65010.h>
#include "common.h"
#include "board-h3.h"
#include "mmc.h"

1
arch/arm/mach-omap1/board-h3.c
View File

@@ -452,6 +452,7 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
.map_io = omap16xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = h3_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-htcherald.c
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@@ -601,6 +601,7 @@ MACHINE_START(HERALD, "HTC Herald")
.map_io = htcherald_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = htcherald_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-innovator.c
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@@ -456,6 +456,7 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
.map_io = innovator_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = innovator_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-nokia770.c
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@@ -294,6 +294,7 @@ MACHINE_START(NOKIA770, "Nokia 770")
.map_io = omap16xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_nokia770_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-osk.c
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@@ -610,6 +610,7 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
.map_io = omap16xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = osk_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-palmte.c
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@@ -235,6 +235,7 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.map_io = omap15xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_palmte_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-palmtt.c
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@@ -282,6 +282,7 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
.map_io = omap15xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_palmtt_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-palmz71.c
View File

@@ -297,6 +297,7 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
.map_io = omap15xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_palmz71_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-perseus2.c
View File

@@ -324,6 +324,7 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
.map_io = omap_perseus2_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_perseus2_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-sx1.c
View File

@@ -343,6 +343,7 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
.map_io = omap15xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = omap_sx1_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

1
arch/arm/mach-omap1/board-voiceblue.c
View File

@@ -288,6 +288,7 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
.map_io = omap15xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = voiceblue_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,

7
arch/arm/mach-omap1/common.h
View File

@@ -30,10 +30,14 @@
#include <linux/i2c-omap.h>
#include <linux/reboot.h>
#include <asm/exception.h>
#include <plat/i2c.h>
#include <mach/irqs.h>
#include "soc.h"
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
void omap7xx_map_io(void);
#else
@@ -73,6 +77,7 @@ static inline int omap_serial_wakeup_init(void)
void omap1_init_early(void);
void omap1_init_irq(void);
void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs);
void omap1_init_late(void);
void omap1_restart(enum reboot_mode, const char *);
@@ -91,8 +96,6 @@ static inline int __init omap_32k_timer_init(void)
}
#endif
extern u32 omap_irq_flags;
#ifdef CONFIG_ARCH_OMAP16XX
extern int ocpi_enable(void);
#else

2
arch/arm/mach-omap1/dma.c
View File

@@ -28,7 +28,7 @@
#include <linux/omap-dma.h>
#include <mach/tc.h>
#include <mach/irqs.h>
#include "soc.h"
#define OMAP1_DMA_BASE (0xfffed800)
#define OMAP1_LOGICAL_DMA_CH_COUNT 17

2
arch/arm/mach-omap1/gpio16xx.c
View File

@@ -21,6 +21,8 @@
#include <mach/irqs.h>
#include "soc.h"
#define OMAP1610_GPIO1_BASE 0xfffbe400
#define OMAP1610_GPIO2_BASE 0xfffbec00
#define OMAP1610_GPIO3_BASE 0xfffbb400

2
arch/arm/mach-omap1/gpio7xx.c
View File

@@ -21,6 +21,8 @@
#include <mach/irqs.h>
#include "soc.h"
#define OMAP7XX_GPIO1_BASE 0xfffbc000
#define OMAP7XX_GPIO2_BASE 0xfffbc800
#define OMAP7XX_GPIO3_BASE 0xfffbd000

3
arch/arm/mach-omap1/i2c.c
View File

@@ -27,7 +27,6 @@
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800
#define OMAP1_INT_I2C (32 + 4)
static const char name[] = "omap_i2c";
@@ -67,7 +66,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
res[0].start = OMAP1_I2C_BASE;
res[0].end = res[0].start + OMAP_I2C_SIZE;
res[0].flags = IORESOURCE_MEM;
res[1].start = OMAP1_INT_I2C;
res[1].start = INT_I2C;
res[1].flags = IORESOURCE_IRQ;
pdev->resource = res;

39
arch/arm/mach-omap1/include/mach/entry-macro.S
View File

@@ -1,39 +0,0 @@
/*
* arch/arm/mach-omap1/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for OMAP-based platforms
*
* Copyright (C) 2009 Texas Instruments
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
#include <mach/irqs.h>
.macro get_irqnr_preamble, base, tmp
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
mov \irqstat, #0xffffffff
bic \tmp, \irqstat, \tmp
tst \irqnr, \tmp
beq 1510f
ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
ldr \tmp, =omap_irq_flags @ irq flags address
ldr \tmp, [\tmp, #0] @ irq flags value
cmp \irqnr, #0
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
cmpeq \irqnr, \tmp
ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
addeqs \irqnr, \irqnr, #32
1510:
.endm

124
arch/arm/mach-omap1/include/mach/irqs.h
View File

@@ -34,84 +34,84 @@
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
*
*/
#define INT_CAMERA 1
#define INT_FIQ 3
#define INT_RTDX 6
#define INT_DSP_MMU_ABORT 7
#define INT_HOST 8
#define INT_ABORT 9
#define INT_BRIDGE_PRIV 13
#define INT_GPIO_BANK1 14
#define INT_UART3 15
#define INT_TIMER3 16
#define INT_DMA_CH0_6 19
#define INT_DMA_CH1_7 20
#define INT_DMA_CH2_8 21
#define INT_DMA_CH3 22
#define INT_DMA_CH4 23
#define INT_DMA_CH5 24
#define INT_TIMER1 26
#define INT_WD_TIMER 27
#define INT_BRIDGE_PUB 28
#define INT_TIMER2 30
#define INT_LCD_CTRL 31
#define INT_CAMERA (NR_IRQS_LEGACY + 1)
#define INT_FIQ (NR_IRQS_LEGACY + 3)
#define INT_RTDX (NR_IRQS_LEGACY + 6)
#define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7)
#define INT_HOST (NR_IRQS_LEGACY + 8)
#define INT_ABORT (NR_IRQS_LEGACY + 9)
#define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13)
#define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14)
#define INT_UART3 (NR_IRQS_LEGACY + 15)
#define INT_TIMER3 (NR_IRQS_LEGACY + 16)
#define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19)
#define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20)
#define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21)
#define INT_DMA_CH3 (NR_IRQS_LEGACY + 22)
#define INT_DMA_CH4 (NR_IRQS_LEGACY + 23)
#define INT_DMA_CH5 (NR_IRQS_LEGACY + 24)
#define INT_TIMER1 (NR_IRQS_LEGACY + 26)
#define INT_WD_TIMER (NR_IRQS_LEGACY + 27)
#define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28)
#define INT_TIMER2 (NR_IRQS_LEGACY + 30)
#define INT_LCD_CTRL (NR_IRQS_LEGACY + 31)
/*
* OMAP-1510 specific IRQ numbers for interrupt handler 1
*/
#define INT_1510_IH2_IRQ 0
#define INT_1510_RES2 2
#define INT_1510_SPI_TX 4
#define INT_1510_SPI_RX 5
#define INT_1510_DSP_MAILBOX1 10
#define INT_1510_DSP_MAILBOX2 11
#define INT_1510_RES12 12
#define INT_1510_LB_MMU 17
#define INT_1510_RES18 18
#define INT_1510_LOCAL_BUS 29
#define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0)
#define INT_1510_RES2 (NR_IRQS_LEGACY + 2)
#define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4)
#define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5)
#define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10)
#define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11)
#define INT_1510_RES12 (NR_IRQS_LEGACY + 12)
#define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17)
#define INT_1510_RES18 (NR_IRQS_LEGACY + 18)
#define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29)
/*
* OMAP-1610 specific IRQ numbers for interrupt handler 1
*/
#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
#define INT_1610_IH2_FIQ 2
#define INT_1610_McBSP2_TX 4
#define INT_1610_McBSP2_RX 5
#define INT_1610_DSP_MAILBOX1 10
#define INT_1610_DSP_MAILBOX2 11
#define INT_1610_LCD_LINE 12
#define INT_1610_GPTIMER1 17
#define INT_1610_GPTIMER2 18
#define INT_1610_SSR_FIFO_0 29
#define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2)
#define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4)
#define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5)
#define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10)
#define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11)
#define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12)
#define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17)
#define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18)
#define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29)
/*
* OMAP-7xx specific IRQ numbers for interrupt handler 1
*/
#define INT_7XX_IH2_FIQ 0
#define INT_7XX_IH2_IRQ 1
#define INT_7XX_USB_NON_ISO 2
#define INT_7XX_USB_ISO 3
#define INT_7XX_ICR 4
#define INT_7XX_EAC 5
#define INT_7XX_GPIO_BANK1 6
#define INT_7XX_GPIO_BANK2 7
#define INT_7XX_GPIO_BANK3 8
#define INT_7XX_McBSP2TX 10
#define INT_7XX_McBSP2RX 11
#define INT_7XX_McBSP2RX_OVF 12
#define INT_7XX_LCD_LINE 14
#define INT_7XX_GSM_PROTECT 15
#define INT_7XX_TIMER3 16
#define INT_7XX_GPIO_BANK5 17
#define INT_7XX_GPIO_BANK6 18
#define INT_7XX_SPGIO_WR 29
#define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0)
#define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1)
#define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2)
#define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3)
#define INT_7XX_ICR (NR_IRQS_LEGACY + 4)
#define INT_7XX_EAC (NR_IRQS_LEGACY + 5)
#define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6)
#define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7)
#define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8)
#define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10)
#define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11)
#define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12)
#define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14)
#define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15)
#define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16)
#define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17)
#define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18)
#define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29)
/*
* IRQ numbers for interrupt handler 2
*
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
*/
#define IH2_BASE 32
#define IH2_BASE (NR_IRQS_LEGACY + 32)
#define INT_KEYBOARD (1 + IH2_BASE)
#define INT_uWireTX (2 + IH2_BASE)
@@ -255,11 +255,7 @@
#endif
#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
#define NR_IRQS OMAP_FPGA_IRQ_END
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
#include <mach/hardware.h>
#define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32))
#ifdef CONFIG_FIQ
#define FIQ_START 1024

4
arch/arm/mach-omap1/include/mach/memory.h
View File

@@ -5,6 +5,9 @@
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/* REVISIT: omap1 legacy drivers still rely on this */
#include <mach/soc.h>
/*
* Bus address is physical address, except for OMAP-1510 Local Bus.
* OMAP-1510 bus address is translated into a Local Bus address if the
@@ -14,7 +17,6 @@
* because of the strncmp().
*/
#if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
#include <mach/soc.h>
/*
* OMAP-1510 Local Bus address offset

5
arch/arm/mach-omap1/include/mach/serial.h
View File

@@ -27,11 +27,6 @@
*/
#define OMAP_UART_INFO_OFS 0x3ffc
/* OMAP1 serial ports */
#define OMAP1_UART1_BASE 0xfffb0000
#define OMAP1_UART2_BASE 0xfffb0800
#define OMAP1_UART3_BASE 0xfffb9800
#define OMAP_PORT_SHIFT 2
#define OMAP7XX_PORT_SHIFT 0

4
arch/arm/mach-omap1/include/mach/soc.h
View File

@@ -28,6 +28,10 @@
#ifndef __ASM_ARCH_OMAP_CPU_H
#define __ASM_ARCH_OMAP_CPU_H
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>

161
arch/arm/mach-omap1/irq.c
View File

@@ -43,6 +43,7 @@
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include "soc.h"
@@ -56,66 +57,41 @@
struct omap_irq_bank {
unsigned long base_reg;
void __iomem *va;
unsigned long trigger_map;
unsigned long wake_enable;
};
u32 omap_irq_flags;
static u32 omap_l2_irq;
static unsigned int irq_bank_count;
static struct omap_irq_bank *irq_banks;
static struct irq_domain *domain;
static inline unsigned int irq_bank_readl(int bank, int offset)
{
return readl_relaxed(irq_banks[bank].va + offset);
}
static inline void irq_bank_writel(unsigned long value, int bank, int offset)
{
omap_writel(value, irq_banks[bank].base_reg + offset);
writel_relaxed(value, irq_banks[bank].va + offset);
}
static void omap_ack_irq(struct irq_data *d)
static void omap_ack_irq(int irq)
{
if (d->irq > 31)
omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
if (irq > 31)
writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET);
omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
}
static void omap_mask_irq(struct irq_data *d)
{
int bank = IRQ_BANK(d->irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l |= 1 << IRQ_BIT(d->irq);
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
}
static void omap_unmask_irq(struct irq_data *d)
{
int bank = IRQ_BANK(d->irq);
u32 l;
l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
l &= ~(1 << IRQ_BIT(d->irq));
omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET);
}
static void omap_mask_ack_irq(struct irq_data *d)
{
omap_mask_irq(d);
omap_ack_irq(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
ct->chip.irq_mask(d);
omap_ack_irq(d->irq);
}
static int omap_wake_irq(struct irq_data *d, unsigned int enable)
{
int bank = IRQ_BANK(d->irq);
if (enable)
irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
else
irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
return 0;
}
/*
* Allows tuning the IRQ type and priority
*
@@ -165,46 +141,105 @@ static struct omap_irq_bank omap1610_irq_banks[] = {
};
#endif
static struct irq_chip omap_irq_chip = {
.name = "MPU",
.irq_ack = omap_mask_ack_irq,
.irq_mask = omap_mask_irq,
.irq_unmask = omap_unmask_irq,
.irq_set_wake = omap_wake_irq,
};
asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs)
{
void __iomem *l1 = irq_banks[0].va;
void __iomem *l2 = irq_banks[1].va;
u32 irqnr;
do {
irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET);
irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff);
if (!irqnr)
break;
irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET);
if (irqnr)
goto irq;
irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET);
if (irqnr == omap_l2_irq) {
irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET);
if (irqnr)
irqnr += 32;
}
irq:
if (irqnr)
handle_domain_irq(domain, irqnr, regs);
else
break;
} while (irqnr);
}
static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("MPU", 1, irq_start, base,
handle_level_irq);
ct = gc->chip_types;
ct->chip.irq_ack = omap_mask_ack_irq;
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_wake = irq_gc_set_wake;
ct->regs.mask = IRQ_MIR_REG_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
void __init omap1_init_irq(void)
{
int i, j;
struct irq_chip_type *ct;
struct irq_data *d = NULL;
int i, j, irq_base;
unsigned long nr_irqs;
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
if (cpu_is_omap7xx()) {
omap_irq_flags = INT_7XX_IH2_IRQ;
irq_banks = omap7xx_irq_banks;
irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
}
if (cpu_is_omap310()) {
omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap310_irq_banks;
irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) {
omap_irq_flags = INT_1510_IH2_IRQ;
irq_banks = omap1610_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
}
#endif
printk("Total of %i interrupts in %i interrupt banks\n",
irq_bank_count * 32, irq_bank_count);
for (i = 0; i < irq_bank_count; i++) {
irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff);
if (WARN_ON(!irq_banks[i].va))
return;
}
nr_irqs = irq_bank_count * 32;
irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
if (irq_base < 0) {
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
}
omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base;
omap_l2_irq -= NR_IRQS_LEGACY;
domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0,
&irq_domain_simple_ops, NULL);
pr_info("Total of %lu interrupts in %i interrupt banks\n",
nr_irqs, irq_bank_count);
/* Mask and clear all interrupts */
for (i = 0; i < irq_bank_count; i++) {
@@ -227,19 +262,15 @@ void __init omap1_init_irq(void)
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger);
irq_set_chip_and_handler(j, &omap_irq_chip,
handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32);
}
/* Unmask level 2 handler */
if (cpu_is_omap7xx())
omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
else if (cpu_is_omap15xx())
omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
else if (cpu_is_omap16xx())
omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq));
if (d) {
ct = irq_data_get_chip_type(d);
ct->chip.irq_unmask(d);
}
}

8
arch/arm/mach-omap1/mux.c
View File

@@ -36,7 +36,7 @@
static struct omap_mux_cfg arch_mux_cfg;
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct pin_config __initdata_or_module omap7xx_pins[] = {
static struct pin_config omap7xx_pins[] = {
MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
@@ -82,7 +82,7 @@ MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0)
#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static struct pin_config __initdata_or_module omap1xxx_pins[] = {
static struct pin_config omap1xxx_pins[] = {
/*
* description mux mode mux pull pull pull pu_pd pu dbg
* reg offset mode reg bit ena reg
@@ -343,7 +343,7 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
#define OMAP1XXX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
static int omap1_cfg_reg(const struct pin_config *cfg)
{
static DEFINE_SPINLOCK(mux_spin_lock);
unsigned long flags;
@@ -469,7 +469,7 @@ int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
/*
* Sets the Omap MUX and PULL_DWN registers based on the table
*/
int __init_or_module omap_cfg_reg(const unsigned long index)
int omap_cfg_reg(const unsigned long index)
{
struct pin_config *reg;

1
arch/arm/mach-omap1/pm.c
View File

@@ -62,6 +62,7 @@
#include "iomap.h"
#include "clock.h"
#include "pm.h"
#include "soc.h"
#include "sram.h"
static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];

1
arch/arm/mach-omap1/serial.c
View File

@@ -25,6 +25,7 @@
#include <mach/mux.h>
#include "pm.h"
#include "soc.h"
static struct clk * uart1_ck;
static struct clk * uart2_ck;

4
arch/arm/mach-omap1/timer.c
View File

@@ -27,10 +27,10 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <mach/irqs.h>
#include <plat/dmtimer.h>
#include "soc.h"
#define OMAP1610_GPTIMER1_BASE 0xfffb1400
#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
#define OMAP1610_GPTIMER3_BASE 0xfffb2400