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ARM: dts: meson8: add support for booting the secondary CPU cores

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Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.

Suggested-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl
2017-09-17 18:45:22 +02:00
committed by Kevin Hilman
parent 88b1b18ffe
commit 4a5a27116b
1 changed files with 21 additions and 0 deletions
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21
arch/arm/boot/dts/meson8.dtsi
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@@ -45,6 +45,7 @@
#include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h> #include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include "meson.dtsi" #include "meson.dtsi"
/ { / {
@@ -60,6 +61,8 @@
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
reg = <0x200>; reg = <0x200>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
}; };
cpu@201 { cpu@201 {
@@ -67,6 +70,8 @@
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
reg = <0x201>; reg = <0x201>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
}; };
cpu@202 { cpu@202 {
@@ -74,6 +79,8 @@
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
reg = <0x202>; reg = <0x202>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
}; };
cpu@203 { cpu@203 {
@@ -81,6 +88,8 @@
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
reg = <0x203>; reg = <0x203>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
}; };
}; };
@@ -118,6 +127,11 @@
}; /* end of / */ }; /* end of / */
&aobus { &aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
reg = <0xe0 0x8>;
};
pinctrl_aobus: pinctrl@84 { pinctrl_aobus: pinctrl@84 {
compatible = "amlogic,meson8-aobus-pinctrl"; compatible = "amlogic,meson8-aobus-pinctrl";
reg = <0x84 0xc>; reg = <0x84 0xc>;
@@ -254,6 +268,13 @@
}; };
}; };
&ahb_sram {
smp-sram@1ff80 {
compatible = "amlogic,meson8-smp-sram";
reg = <0x1ff80 0x8>;
};
};
&ethmac { &ethmac {
clocks = <&clkc CLKID_ETH>; clocks = <&clkc CLKID_ETH>;
clock-names = "stmmaceth"; clock-names = "stmmaceth";