net: sh_eth: modify the definitions of register
The previous code cannot handle the ETHER and GETHER both as same time because the definitions of register was hardcoded. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yoshihiro Shimoda
committed by
David S. Miller
David S. Miller
parent
201a11c1db
commit
4a55530f38
@@ -2,7 +2,7 @@
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* SuperH Ethernet device driver
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*
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* Copyright (C) 2006-2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008-2009 Renesas Solutions Corp.
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* Copyright (C) 2008-2011 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -38,162 +38,345 @@
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#define ETHERSMALL 60
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#define PKT_BUF_SZ 1538
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enum {
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/* E-DMAC registers */
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EDSR = 0,
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EDMR,
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EDTRR,
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EDRRR,
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EESR,
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EESIPR,
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TDLAR,
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TDFAR,
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TDFXR,
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TDFFR,
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RDLAR,
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RDFAR,
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RDFXR,
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RDFFR,
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TRSCER,
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RMFCR,
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TFTR,
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FDR,
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RMCR,
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EDOCR,
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TFUCR,
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RFOCR,
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FCFTR,
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RPADIR,
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TRIMD,
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RBWAR,
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TBRAR,
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/* Ether registers */
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ECMR,
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ECSR,
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ECSIPR,
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PIR,
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PSR,
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RDMLR,
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PIPR,
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RFLR,
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IPGR,
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APR,
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MPR,
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PFTCR,
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PFRCR,
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RFCR,
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RFCF,
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TPAUSER,
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TPAUSECR,
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BCFR,
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BCFRR,
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GECMR,
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BCULR,
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MAHR,
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MALR,
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TROCR,
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CDCR,
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LCCR,
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CNDCR,
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CEFCR,
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FRECR,
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TSFRCR,
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TLFRCR,
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CERCR,
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CEECR,
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MAFCR,
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RTRATE,
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/* TSU Absolute address */
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ARSTR,
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TSU_CTRST,
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TSU_FWEN0,
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TSU_FWEN1,
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TSU_FCM,
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TSU_BSYSL0,
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TSU_BSYSL1,
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TSU_PRISL0,
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TSU_PRISL1,
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TSU_FWSL0,
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TSU_FWSL1,
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TSU_FWSLC,
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TSU_QTAG0,
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TSU_QTAG1,
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TSU_QTAGM0,
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TSU_QTAGM1,
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TSU_FWSR,
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TSU_FWINMK,
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TSU_ADQT0,
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TSU_ADQT1,
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TSU_VTAG0,
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TSU_VTAG1,
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TSU_ADSBSY,
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TSU_TEN,
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TSU_POST1,
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TSU_POST2,
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TSU_POST3,
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TSU_POST4,
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TSU_ADRH0,
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TSU_ADRL0,
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TSU_ADRH31,
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TSU_ADRL31,
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TXNLCR0,
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TXALCR0,
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RXNLCR0,
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RXALCR0,
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FWNLCR0,
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FWALCR0,
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TXNLCR1,
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TXALCR1,
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RXNLCR1,
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RXALCR1,
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FWNLCR1,
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FWALCR1,
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/* This value must be written at last. */
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SH_ETH_MAX_REGISTER_OFFSET,
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};
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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[ECMR] = 0x0500,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[PSR] = 0x0528,
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[PIPR] = 0x052c,
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[RFLR] = 0x0508,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[GECMR] = 0x05b0,
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[BCULR] = 0x05b4,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[TROCR] = 0x0700,
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[CDCR] = 0x0708,
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[LCCR] = 0x0710,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[CERCR] = 0x0768,
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[CEECR] = 0x0770,
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[MAFCR] = 0x0778,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAG0] = 0x0040,
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[TSU_QTAG1] = 0x0044,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_VTAG0] = 0x0058,
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[TSU_VTAG1] = 0x005c,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRH31] = 0x01f8,
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[TSU_ADRL31] = 0x01fc,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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};
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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0100,
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[RFLR] = 0x0108,
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[ECSR] = 0x0110,
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[ECSIPR] = 0x0118,
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[PIR] = 0x0120,
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[PSR] = 0x0128,
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[RDMLR] = 0x0140,
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[IPGR] = 0x0150,
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[APR] = 0x0154,
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[MPR] = 0x0158,
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[TPAUSER] = 0x0164,
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[RFCF] = 0x0160,
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[TPAUSECR] = 0x0168,
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[BCFRR] = 0x016c,
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[MAHR] = 0x01c0,
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[MALR] = 0x01c8,
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[TROCR] = 0x01d0,
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[CDCR] = 0x01d4,
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[LCCR] = 0x01d8,
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[CNDCR] = 0x01dc,
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[CEFCR] = 0x01e4,
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[FRECR] = 0x01e8,
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[TSFRCR] = 0x01ec,
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[TLFRCR] = 0x01f0,
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[RFCR] = 0x01f4,
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[MAFCR] = 0x01f8,
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[RTRATE] = 0x01fc,
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[EDMR] = 0x0000,
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[EDTRR] = 0x0008,
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[EDRRR] = 0x0010,
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[TDLAR] = 0x0018,
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[RDLAR] = 0x0020,
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[EESR] = 0x0028,
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[EESIPR] = 0x0030,
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[TRSCER] = 0x0038,
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[RMFCR] = 0x0040,
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[TFTR] = 0x0048,
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[FDR] = 0x0050,
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[RMCR] = 0x0058,
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[TFUCR] = 0x0064,
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[RFOCR] = 0x0068,
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[FCFTR] = 0x0070,
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[RPADIR] = 0x0078,
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[TRIMD] = 0x007c,
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[RBWAR] = 0x00c8,
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[RDFAR] = 0x00cc,
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[TBRAR] = 0x00d4,
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[TDFAR] = 0x00d8,
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};
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static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0160,
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[ECSR] = 0x0164,
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[ECSIPR] = 0x0168,
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[PIR] = 0x016c,
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[MAHR] = 0x0170,
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[MALR] = 0x0174,
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[RFLR] = 0x0178,
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[PSR] = 0x017c,
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[TROCR] = 0x0180,
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[CDCR] = 0x0184,
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[LCCR] = 0x0188,
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[CNDCR] = 0x018c,
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[CEFCR] = 0x0194,
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[FRECR] = 0x0198,
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[TSFRCR] = 0x019c,
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[TLFRCR] = 0x01a0,
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[RFCR] = 0x01a4,
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[MAFCR] = 0x01a8,
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[IPGR] = 0x01b4,
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[APR] = 0x01b8,
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[MPR] = 0x01bc,
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[TPAUSER] = 0x01c4,
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[BCFR] = 0x01cc,
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[TSU_CTRST] = 0x0004,
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[TSU_FWEN0] = 0x0010,
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[TSU_FWEN1] = 0x0014,
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[TSU_FCM] = 0x0018,
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[TSU_BSYSL0] = 0x0020,
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[TSU_BSYSL1] = 0x0024,
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[TSU_PRISL0] = 0x0028,
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[TSU_PRISL1] = 0x002c,
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAGM0] = 0x0040,
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[TSU_QTAGM1] = 0x0044,
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[TSU_ADQT0] = 0x0048,
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[TSU_ADQT1] = 0x004c,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADSBSY] = 0x0060,
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[TSU_TEN] = 0x0064,
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[TSU_POST1] = 0x0070,
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[TSU_POST2] = 0x0074,
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[TSU_POST3] = 0x0078,
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[TSU_POST4] = 0x007c,
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[TXNLCR0] = 0x0080,
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[TXALCR0] = 0x0084,
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[RXNLCR0] = 0x0088,
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[RXALCR0] = 0x008c,
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[FWNLCR0] = 0x0090,
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[FWALCR0] = 0x0094,
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[TXNLCR1] = 0x00a0,
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[TXALCR1] = 0x00a0,
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[RXNLCR1] = 0x00a8,
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[RXALCR1] = 0x00ac,
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[FWNLCR1] = 0x00b0,
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[FWALCR1] = 0x00b4,
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[TSU_ADRH0] = 0x0100,
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[TSU_ADRL0] = 0x0104,
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[TSU_ADRL31] = 0x01fc,
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};
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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/* This CPU register maps is very difference by other SH4 CPU */
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/* Chip Base Address */
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# define SH_TSU_ADDR 0xFEE01800
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# define ARSTR SH_TSU_ADDR
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/* Chip Registers */
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/* E-DMAC */
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# define EDSR 0x000
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# define EDMR 0x400
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# define EDTRR 0x408
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# define EDRRR 0x410
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# define EESR 0x428
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# define EESIPR 0x430
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# define TDLAR 0x010
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# define TDFAR 0x014
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# define TDFXR 0x018
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# define TDFFR 0x01C
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# define RDLAR 0x030
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# define RDFAR 0x034
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# define RDFXR 0x038
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# define RDFFR 0x03C
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# define TRSCER 0x438
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# define RMFCR 0x440
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# define TFTR 0x448
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# define FDR 0x450
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# define RMCR 0x458
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# define RPADIR 0x460
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# define FCFTR 0x468
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/* Ether Register */
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# define ECMR 0x500
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# define ECSR 0x510
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# define ECSIPR 0x518
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# define PIR 0x520
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# define PSR 0x528
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# define PIPR 0x52C
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# define RFLR 0x508
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# define APR 0x554
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# define MPR 0x558
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# define PFTCR 0x55C
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# define PFRCR 0x560
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# define TPAUSER 0x564
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# define GECMR 0x5B0
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# define BCULR 0x5B4
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# define MAHR 0x5C0
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# define MALR 0x5C8
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# define TROCR 0x700
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# define CDCR 0x708
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# define LCCR 0x710
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# define CEFCR 0x740
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# define FRECR 0x748
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# define TSFRCR 0x750
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# define TLFRCR 0x758
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# define RFCR 0x760
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# define CERCR 0x768
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# define CEECR 0x770
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# define MAFCR 0x778
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/* TSU Absolute Address */
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# define TSU_CTRST 0x004
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# define TSU_FWEN0 0x010
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# define TSU_FWEN1 0x014
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# define TSU_FCM 0x18
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# define TSU_BSYSL0 0x20
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# define TSU_BSYSL1 0x24
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# define TSU_PRISL0 0x28
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# define TSU_PRISL1 0x2C
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# define TSU_FWSL0 0x30
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# define TSU_FWSL1 0x34
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# define TSU_FWSLC 0x38
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# define TSU_QTAG0 0x40
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# define TSU_QTAG1 0x44
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# define TSU_FWSR 0x50
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# define TSU_FWINMK 0x54
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# define TSU_ADQT0 0x48
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# define TSU_ADQT1 0x4C
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# define TSU_VTAG0 0x58
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# define TSU_VTAG1 0x5C
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# define TSU_ADSBSY 0x60
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# define TSU_TEN 0x64
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# define TSU_POST1 0x70
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# define TSU_POST2 0x74
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# define TSU_POST3 0x78
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# define TSU_POST4 0x7C
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# define TSU_ADRH0 0x100
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# define TSU_ADRL0 0x104
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# define TSU_ADRH31 0x1F8
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# define TSU_ADRL31 0x1FC
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# define TXNLCR0 0x80
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# define TXALCR0 0x84
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# define RXNLCR0 0x88
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# define RXALCR0 0x8C
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# define FWNLCR0 0x90
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# define FWALCR0 0x94
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# define TXNLCR1 0xA0
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# define TXALCR1 0xA4
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# define RXNLCR1 0xA8
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# define RXALCR1 0xAC
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# define FWNLCR1 0xB0
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# define FWALCR1 0x40
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#elif defined(CONFIG_CPU_SH4) /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */
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/* EtherC */
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#define ECMR 0x100
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||||
#define RFLR 0x108
|
||||
#define ECSR 0x110
|
||||
#define ECSIPR 0x118
|
||||
#define PIR 0x120
|
||||
#define PSR 0x128
|
||||
#define RDMLR 0x140
|
||||
#define IPGR 0x150
|
||||
#define APR 0x154
|
||||
#define MPR 0x158
|
||||
#define TPAUSER 0x164
|
||||
#define RFCF 0x160
|
||||
#define TPAUSECR 0x168
|
||||
#define BCFRR 0x16c
|
||||
#define MAHR 0x1c0
|
||||
#define MALR 0x1c8
|
||||
#define TROCR 0x1d0
|
||||
#define CDCR 0x1d4
|
||||
#define LCCR 0x1d8
|
||||
#define CNDCR 0x1dc
|
||||
#define CEFCR 0x1e4
|
||||
#define FRECR 0x1e8
|
||||
#define TSFRCR 0x1ec
|
||||
#define TLFRCR 0x1f0
|
||||
#define RFCR 0x1f4
|
||||
#define MAFCR 0x1f8
|
||||
#define RTRATE 0x1fc
|
||||
|
||||
/* E-DMAC */
|
||||
#define EDMR 0x000
|
||||
#define EDTRR 0x008
|
||||
#define EDRRR 0x010
|
||||
#define TDLAR 0x018
|
||||
#define RDLAR 0x020
|
||||
#define EESR 0x028
|
||||
#define EESIPR 0x030
|
||||
#define TRSCER 0x038
|
||||
#define RMFCR 0x040
|
||||
#define TFTR 0x048
|
||||
#define FDR 0x050
|
||||
#define RMCR 0x058
|
||||
#define TFUCR 0x064
|
||||
#define RFOCR 0x068
|
||||
#define FCFTR 0x070
|
||||
#define RPADIR 0x078
|
||||
#define TRIMD 0x07c
|
||||
#define RBWAR 0x0c8
|
||||
#define RDFAR 0x0cc
|
||||
#define TBRAR 0x0d4
|
||||
#define TDFAR 0x0d8
|
||||
#else /* #elif defined(CONFIG_CPU_SH4) */
|
||||
/* This section is SH3 or SH2 */
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7619
|
||||
@@ -201,116 +384,8 @@
|
||||
# define SH_TSU_ADDR 0xA7000804
|
||||
# define ARSTR 0xA7000800
|
||||
#endif
|
||||
/* Chip Registers */
|
||||
/* E-DMAC */
|
||||
# define EDMR 0x0000
|
||||
# define EDTRR 0x0004
|
||||
# define EDRRR 0x0008
|
||||
# define TDLAR 0x000C
|
||||
# define RDLAR 0x0010
|
||||
# define EESR 0x0014
|
||||
# define EESIPR 0x0018
|
||||
# define TRSCER 0x001C
|
||||
# define RMFCR 0x0020
|
||||
# define TFTR 0x0024
|
||||
# define FDR 0x0028
|
||||
# define RMCR 0x002C
|
||||
# define EDOCR 0x0030
|
||||
# define FCFTR 0x0034
|
||||
# define RPADIR 0x0038
|
||||
# define TRIMD 0x003C
|
||||
# define RBWAR 0x0040
|
||||
# define RDFAR 0x0044
|
||||
# define TBRAR 0x004C
|
||||
# define TDFAR 0x0050
|
||||
|
||||
/* Ether Register */
|
||||
# define ECMR 0x0160
|
||||
# define ECSR 0x0164
|
||||
# define ECSIPR 0x0168
|
||||
# define PIR 0x016C
|
||||
# define MAHR 0x0170
|
||||
# define MALR 0x0174
|
||||
# define RFLR 0x0178
|
||||
# define PSR 0x017C
|
||||
# define TROCR 0x0180
|
||||
# define CDCR 0x0184
|
||||
# define LCCR 0x0188
|
||||
# define CNDCR 0x018C
|
||||
# define CEFCR 0x0194
|
||||
# define FRECR 0x0198
|
||||
# define TSFRCR 0x019C
|
||||
# define TLFRCR 0x01A0
|
||||
# define RFCR 0x01A4
|
||||
# define MAFCR 0x01A8
|
||||
# define IPGR 0x01B4
|
||||
# if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
# define APR 0x01B8
|
||||
# define MPR 0x01BC
|
||||
# define TPAUSER 0x1C4
|
||||
# define BCFR 0x1CC
|
||||
# endif /* CONFIG_CPU_SH7710 */
|
||||
|
||||
/* TSU */
|
||||
# define TSU_CTRST 0x004
|
||||
# define TSU_FWEN0 0x010
|
||||
# define TSU_FWEN1 0x014
|
||||
# define TSU_FCM 0x018
|
||||
# define TSU_BSYSL0 0x020
|
||||
# define TSU_BSYSL1 0x024
|
||||
# define TSU_PRISL0 0x028
|
||||
# define TSU_PRISL1 0x02C
|
||||
# define TSU_FWSL0 0x030
|
||||
# define TSU_FWSL1 0x034
|
||||
# define TSU_FWSLC 0x038
|
||||
# define TSU_QTAGM0 0x040
|
||||
# define TSU_QTAGM1 0x044
|
||||
# define TSU_ADQT0 0x048
|
||||
# define TSU_ADQT1 0x04C
|
||||
# define TSU_FWSR 0x050
|
||||
# define TSU_FWINMK 0x054
|
||||
# define TSU_ADSBSY 0x060
|
||||
# define TSU_TEN 0x064
|
||||
# define TSU_POST1 0x070
|
||||
# define TSU_POST2 0x074
|
||||
# define TSU_POST3 0x078
|
||||
# define TSU_POST4 0x07C
|
||||
# define TXNLCR0 0x080
|
||||
# define TXALCR0 0x084
|
||||
# define RXNLCR0 0x088
|
||||
# define RXALCR0 0x08C
|
||||
# define FWNLCR0 0x090
|
||||
# define FWALCR0 0x094
|
||||
# define TXNLCR1 0x0A0
|
||||
# define TXALCR1 0x0A4
|
||||
# define RXNLCR1 0x0A8
|
||||
# define RXALCR1 0x0AC
|
||||
# define FWNLCR1 0x0B0
|
||||
# define FWALCR1 0x0B4
|
||||
|
||||
#define TSU_ADRH0 0x0100
|
||||
#define TSU_ADRL0 0x0104
|
||||
#define TSU_ADRL31 0x01FC
|
||||
|
||||
#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
|
||||
|
||||
/* There are avoid compile error... */
|
||||
#if !defined(BCULR)
|
||||
#define BCULR 0x0fc
|
||||
#endif
|
||||
#if !defined(TRIMD)
|
||||
#define TRIMD 0x0fc
|
||||
#endif
|
||||
#if !defined(APR)
|
||||
#define APR 0x0fc
|
||||
#endif
|
||||
#if !defined(MPR)
|
||||
#define MPR 0x0fc
|
||||
#endif
|
||||
#if !defined(TPAUSER)
|
||||
#define TPAUSER 0x0fc
|
||||
#endif
|
||||
|
||||
/* Driver's parameters */
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
#define SH4_SKB_RX_ALIGN 32
|
||||
@@ -704,6 +779,8 @@ struct sh_eth_cpu_data {
|
||||
struct sh_eth_private {
|
||||
struct platform_device *pdev;
|
||||
struct sh_eth_cpu_data *cd;
|
||||
const u16 *reg_offset;
|
||||
void __iomem *tsu_addr;
|
||||
dma_addr_t rx_desc_dma;
|
||||
dma_addr_t tx_desc_dma;
|
||||
struct sh_eth_rxdesc *rx_ring;
|
||||
@@ -746,4 +823,32 @@ static inline void sh_eth_soft_swap(char *src, int len)
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
|
||||
int enum_index)
|
||||
{
|
||||
struct sh_eth_private *mdp = netdev_priv(ndev);
|
||||
|
||||
writel(data, ndev->base_addr + mdp->reg_offset[enum_index]);
|
||||
}
|
||||
|
||||
static inline unsigned long sh_eth_read(struct net_device *ndev,
|
||||
int enum_index)
|
||||
{
|
||||
struct sh_eth_private *mdp = netdev_priv(ndev);
|
||||
|
||||
return readl(ndev->base_addr + mdp->reg_offset[enum_index]);
|
||||
}
|
||||
|
||||
static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
|
||||
unsigned long data, int enum_index)
|
||||
{
|
||||
writel(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
|
||||
}
|
||||
|
||||
static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
|
||||
int enum_index)
|
||||
{
|
||||
return readl(mdp->tsu_addr + mdp->reg_offset[enum_index]);
|
||||
}
|
||||
|
||||
#endif /* #ifndef __SH_ETH_H__ */
|
||||
|
||||
Reference in New Issue
Block a user