Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, these contain various things that touch the drivers/ directory but got merged through arm-soc for practical reasons. For the most part, this is now related to power management controllers, which have not yet been abstracted into a separate subsystem, and typically require some code in drivers/soc or arch/arm to control the power domains. Another large chunk here is a rework of the NVIDIA Tegra USB3.0 support, which was surprisingly tricky and took a long time to get done. Finally, reset controller handling as always gets merged through here as well" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) arm-ccn: Enable building as module soc/tegra: pmc: Add generic PM domain support usb: xhci: tegra: Add Tegra210 support usb: xhci: Add NVIDIA Tegra XUSB controller driver dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs drivers: firmware: psci: make two helper functions inline soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas ...
此提交包含在：
Linus Torvalds
@@ -18,6 +18,7 @@ menuconfig ARCH_EXYNOS
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select COMMON_CLK_SAMSUNG
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select EXYNOS_THERMAL
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select EXYNOS_PMU
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select EXYNOS_SROM
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select HAVE_ARM_SCU if SMP
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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@@ -26,11 +27,13 @@ menuconfig ARCH_EXYNOS
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select S5P_DEV_MFC
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select SAMSUNG_MC
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select SOC_SAMSUNG
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select SRAM
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select THERMAL
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select THERMAL_OF
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select MFD_SYSCON
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select MEMORY
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select CLKSRC_EXYNOS_MCT
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select POWER_RESET
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select POWER_RESET_SYSCON
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@@ -31,11 +31,6 @@
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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.length = SZ_128K,
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@@ -58,15 +53,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
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},
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};
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static struct map_desc exynos5_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static struct platform_device exynos_cpuidle = {
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.name = "exynos_cpuidle",
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#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
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@@ -138,9 +124,6 @@ static void __init exynos_map_io(void)
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{
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if (soc_is_exynos4())
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iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
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if (soc_is_exynos5())
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iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
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}
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static void __init exynos_init_io(void)
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@@ -25,7 +25,4 @@
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#define EXYNOS4_PA_COREPERI 0x10500000
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS5_PA_SROMC 0x12250000
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#endif /* __ASM_ARCH_MAP_H */
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@@ -1,53 +0,0 @@
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/*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P SROMC register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_SAMSUNG_REGS_SROM_H
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#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
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#include <mach/map.h>
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#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
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#define S5P_SROM_BW S5P_SROMREG(0x0)
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#define S5P_SROM_BC0 S5P_SROMREG(0x4)
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#define S5P_SROM_BC1 S5P_SROMREG(0x8)
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#define S5P_SROM_BC2 S5P_SROMREG(0xc)
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#define S5P_SROM_BC3 S5P_SROMREG(0x10)
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#define S5P_SROM_BC4 S5P_SROMREG(0x14)
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#define S5P_SROM_BC5 S5P_SROMREG(0x18)
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/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
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#define S5P_SROM_BW__DATAWIDTH__SHIFT 0
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#define S5P_SROM_BW__ADDRMODE__SHIFT 1
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#define S5P_SROM_BW__WAITENABLE__SHIFT 2
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#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
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#define S5P_SROM_BW__CS_MASK 0xf
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#define S5P_SROM_BW__NCS0__SHIFT 0
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#define S5P_SROM_BW__NCS1__SHIFT 4
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#define S5P_SROM_BW__NCS2__SHIFT 8
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#define S5P_SROM_BW__NCS3__SHIFT 12
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#define S5P_SROM_BW__NCS4__SHIFT 16
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#define S5P_SROM_BW__NCS5__SHIFT 20
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/* applies to same to BCS0 - BCS3 */
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#define S5P_SROM_BCX__PMC__SHIFT 0
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#define S5P_SROM_BCX__TACP__SHIFT 4
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#define S5P_SROM_BCX__TCAH__SHIFT 8
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#define S5P_SROM_BCX__TCOH__SHIFT 12
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#define S5P_SROM_BCX__TACC__SHIFT 16
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#define S5P_SROM_BCX__TCOS__SHIFT 24
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#define S5P_SROM_BCX__TACS__SHIFT 28
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#endif /* __PLAT_SAMSUNG_REGS_SROM_H */
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@@ -34,10 +34,11 @@
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <mach/map.h>
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#include <plat/pm-common.h>
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#include "common.h"
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#include "regs-srom.h"
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#define REG_TABLE_END (-1U)
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@@ -53,15 +54,6 @@ struct exynos_wkup_irq {
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u32 mask;
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};
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static struct sleep_save exynos_core_save[] = {
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/* SROM side */
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SAVE_ITEM(S5P_SROM_BW),
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SAVE_ITEM(S5P_SROM_BC0),
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SAVE_ITEM(S5P_SROM_BC1),
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SAVE_ITEM(S5P_SROM_BC2),
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SAVE_ITEM(S5P_SROM_BC3),
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};
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struct exynos_pm_data {
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const struct exynos_wkup_irq *wkup_irq;
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unsigned int wake_disable_mask;
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@@ -343,8 +335,6 @@ static void exynos_pm_prepare(void)
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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@@ -375,8 +365,6 @@ static void exynos5420_pm_prepare(void)
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
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/*
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* The cpu state needs to be saved and restored so that the
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@@ -467,8 +455,6 @@ static void exynos_pm_resume(void)
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/* For release retention */
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exynos_pm_release_retention();
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (cpuid == ARM_CPU_PART_CORTEX_A9)
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scu_enable(S5P_VA_SCU);
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@@ -535,8 +521,6 @@ static void exynos5420_pm_resume(void)
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pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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early_wakeup:
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tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
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