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mmc: msm_sdcc: Use MCI_INT_MASK0 for PIO interrupts

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Not all targets have IRQ1 line routed from the SD controller to
the processor. So we cannot rely on IRQ1 for PIO interrupts.
This patch moves all PIO interrupts to IRQ0 and enables the PIO
mode.

Signed-off-by: Murali Palnati <palnatim@codeaurora.org>
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Sahitya Tummala
2011-05-02 18:09:18 +05:30
committed by Chris Ball
parent 4a92fe80be
commit 4a268e0879
2 changed files with 21 additions and 4 deletions
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5
drivers/mmc/host/msm_sdcc.h
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@@ -140,6 +140,11 @@
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK|MCI_PROGDONEMASK)
#define MCI_IRQ_PIO \
(MCI_RXDATAAVLBLMASK | MCI_TXDATAAVLBLMASK | MCI_RXFIFOEMPTYMASK | \
MCI_TXFIFOEMPTYMASK | MCI_RXFIFOFULLMASK | MCI_TXFIFOFULLMASK | \
MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK | \
MCI_RXACTIVEMASK | MCI_TXACTIVEMASK)
/*
* The size of the FIFO in bytes.
*/