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MIPS: features: Add initial support for Segmentation Control registers

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MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
This commit is contained in:
Steven J. Hill
2013-11-14 16:12:24 +00:00
committed by Ralf Baechle
parent 1745c1ef88
commit 4a0156fbfb
4 changed files with 36 additions and 0 deletions
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arch/mips/include/asm/cpu.h
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@@ -352,6 +352,7 @@ enum cpu_type_enum {
#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
/*
* CPU ASE encodings