Merge branch 'pci/host-probe-refactor'
- Use pci_host_bridge.windows list directly instead of splicing in a temporary list for cadence, mvebu, host-common (Rob Herring) - Use pci_host_probe() instead of open-coding all the pieces for altera, brcmstb, iproc, mobiveil, rcar, rockchip, tegra, v3, versatile, xgene, xilinx, xilinx-nwl (Rob Herring) - Convert to devm_platform_ioremap_resource_byname() instead of open-coding platform_get_resource_byname() and devm_ioremap_resource() for altera, cadence, mediatek, rockchip, tegra, xgene (Dejin Zheng) - Convert to devm_platform_ioremap_resource() instead of open-coding platform_get_resource() and devm_ioremap_resource() for aardvark, brcmstb, exynos, ftpci100, versatile (Dejin Zheng) - Remove redundant error messages from devm_pci_remap_cfg_resource() callers (Dejin Zheng) - Drop useless PCI_ENABLE_PROC_DOMAINS from versatile driver (Rob Herring) - Default host bridge parent device to the platform device (Rob Herring) - Drop unnecessary zeroing of host bridge fields (Rob Herring) - Use pci_is_root_bus() instead of tracking root bus number separately in aardvark, designware (imx6, keystone, designware-host), mobiveil, xilinx-nwl, xilinx, rockchip, rcar (Rob Herring) - Set host bridge bus number in pci_scan_root_bus_bridge() instead of each driver for aardvark, designware-host, host-common, mediatek, rcar, tegra, v3-semi (Rob Herring) - Use bridge resources instead of parsing DT 'ranges' again for cadence (Rob Herring) - Remove private bus number and range from cadence (Rob Herring) - Use devm_pci_alloc_host_bridge() to simplify rcar (Rob Herring) - Use struct pci_host_bridge.windows list directly rather than a temporary (Rob Herring) - Reduce OF "missing non-prefetchable window" from error to warning message (Rob Herring) - Convert rcar-gen2 from old Arm-specific pci_common_init_dev() to new arch-independent interfaces (Rob Herring) - Move DT resource setup into devm_pci_alloc_host_bridge() (Rob Herring) - Set bridge map_irq and swizzle_irq to default functions; drivers that don't support legacy IRQs (iproc) need to undo this (Rob Herring) * pci/host-probe-refactor: PCI: Set bridge map_irq and swizzle_irq to default functions PCI: Move DT resource setup into devm_pci_alloc_host_bridge() PCI: rcar-gen2: Convert to use modern host bridge probe functions PCI: of: Reduce missing non-prefetchable memory region to a warning PCI: rcar: Use struct pci_host_bridge.windows list directly PCI: rcar: Use devm_pci_alloc_host_bridge() PCI: cadence: Remove private bus number and range storage PCI: cadence: Use bridge resources for outbound window setup PCI: Move setting pci_host_bridge.busnr out of host drivers PCI: rcar: Use pci_is_root_bus() to check if bus is root bus PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus PCI: designware: Use pci_is_root_bus() to check if bus is root bus PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus PCI: Drop unnecessary zeroing of bridge fields PCI: Set default bridge parent device PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS PCI: controller: Remove duplicate error message PCI: controller: Convert to devm_platform_ioremap_resource() PCI: controller: Convert to devm_platform_ioremap_resource_byname() PCI: xilinx: Use pci_host_probe() to register host PCI: xilinx-nwl: Use pci_host_probe() to register host PCI: rockchip: Use pci_host_probe() to register host PCI: rcar: Use pci_host_probe() to register host PCI: iproc: Use pci_host_probe() to register host PCI: altera: Use pci_host_probe() to register host PCI: xgene: Use pci_host_probe() to register host PCI: versatile: Use pci_host_probe() to register host PCI: v3: Use pci_host_probe() to register host PCI: tegra: Use pci_host_probe() to register host PCI: mobiveil: Use pci_host_probe() to register host PCI: brcmstb: Use pci_host_probe() to register host PCI: host-common: Use struct pci_host_bridge.windows list directly PCI: mvebu: Use struct pci_host_bridge.windows list directly PCI: cadence: Use struct pci_host_bridge.windows list directly # Conflicts: # drivers/pci/controller/cadence/pcie-cadence-host.c
This commit is contained in:
Bjorn Helgaas
@@ -245,11 +245,7 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
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static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
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struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
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unsigned int busn = bus->number;
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if (busn == rc->bus_range->start)
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if (pci_is_root_bus(bus))
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return pci_generic_config_read32(bus, devfn, where, size,
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value);
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@@ -259,11 +255,7 @@ static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
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static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
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struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
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unsigned int busn = bus->number;
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if (busn == rc->bus_range->start)
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if (pci_is_root_bus(bus))
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return pci_generic_config_write32(bus, devfn, where, size,
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value);
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@@ -161,7 +161,7 @@ static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
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return -EINVAL;
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}
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cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
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cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size);
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set_bit(r, &ep->ob_region_map);
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ep->ob_addr[r] = addr;
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@@ -289,7 +289,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
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if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
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ep->irq_pci_fn != fn)) {
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/* First region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, 0,
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cdns_pcie_set_outbound_region_for_normal_msg(pcie, 0, fn, 0,
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ep->irq_phys_addr);
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ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
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ep->irq_pci_fn = fn;
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@@ -370,7 +370,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
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if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
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ep->irq_pci_fn != fn)) {
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/* First region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region(pcie, fn, 0,
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cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
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false,
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ep->irq_phys_addr,
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pci_addr & ~pci_addr_mask,
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@@ -415,7 +415,7 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn,
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if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) ||
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ep->irq_pci_fn != fn) {
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/* First region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region(pcie, fn, 0,
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cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
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false,
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ep->irq_phys_addr,
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msg_addr & ~pci_addr_mask,
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@@ -518,8 +518,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
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pcie->is_rc = false;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
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pcie->reg_base = devm_ioremap_resource(dev, res);
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pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
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if (IS_ERR(pcie->reg_base)) {
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dev_err(dev, "missing \"reg\"\n");
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return PTR_ERR(pcie->reg_base);
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@@ -32,7 +32,7 @@ void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
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unsigned int busn = bus->number;
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u32 addr0, desc0;
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if (busn == rc->bus_range->start) {
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if (pci_is_root_bus(bus)) {
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/*
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* Only the root port (devfn == 0) is connected to this bus.
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* All other PCI devices are behind some bridge hence on another
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@@ -62,7 +62,7 @@ void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
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* The bus number was already set once for all in desc1 by
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* cdns_pcie_host_init_address_translation().
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*/
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if (busn == rc->bus_range->start + 1)
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if (busn == bridge->busnr + 1)
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
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else
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
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@@ -321,10 +321,9 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
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resource_list_for_each_entry(entry, &bridge->dma_ranges) {
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err = cdns_pcie_host_bar_config(rc, entry);
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if (err) {
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if (err)
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dev_err(dev, "Fail to configure IB using dma-ranges\n");
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return err;
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}
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return err;
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}
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return 0;
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@@ -333,15 +332,16 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
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static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
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{
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struct cdns_pcie *pcie = &rc->pcie;
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struct resource *bus_range = rc->bus_range;
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);
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struct resource *cfg_res = rc->cfg_res;
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struct device *dev = pcie->dev;
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struct device_node *np = dev->of_node;
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struct of_pci_range_parser parser;
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struct resource_entry *entry;
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u64 cpu_addr = cfg_res->start;
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struct of_pci_range range;
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u32 addr0, addr1, desc1;
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int r, err;
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int r, err, busnr = 0;
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entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
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if (entry)
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busnr = entry->res->start;
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/*
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* Reserve region 0 for PCI configure space accesses:
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@@ -349,7 +349,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
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* cdns_pci_map_bus(), other region registers are set here once for all.
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*/
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addr1 = 0; /* Should be programmed to zero. */
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desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);
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desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
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@@ -362,25 +362,24 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
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err = of_pci_range_parser_init(&parser, np);
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if (err)
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return err;
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r = 1;
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for_each_of_pci_range(&parser, &range) {
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bool is_io;
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resource_list_for_each_entry(entry, &bridge->windows) {
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struct resource *res = entry->res;
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u64 pci_addr = res->start - entry->offset;
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if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
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is_io = false;
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else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
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is_io = true;
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if (resource_type(res) == IORESOURCE_IO)
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cdns_pcie_set_outbound_region(pcie, busnr, 0, r,
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true,
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pci_pio_to_address(res->start),
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pci_addr,
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resource_size(res));
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else
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continue;
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cdns_pcie_set_outbound_region(pcie, busnr, 0, r,
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false,
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res->start,
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pci_addr,
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resource_size(res));
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cdns_pcie_set_outbound_region(pcie, 0, r, is_io,
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range.cpu_addr,
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range.pci_addr,
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range.size);
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r++;
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}
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@@ -392,39 +391,15 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
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}
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static int cdns_pcie_host_init(struct device *dev,
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struct list_head *resources,
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struct cdns_pcie_rc *rc)
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{
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struct resource *bus_range = NULL;
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struct pci_host_bridge *bridge;
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int err;
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bridge = pci_host_bridge_from_priv(rc);
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if (!bridge)
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return -ENOMEM;
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/* Parse our PCI ranges and request their resources */
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err = pci_parse_request_of_pci_ranges(dev, resources,
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&bridge->dma_ranges, &bus_range);
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if (err)
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return err;
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rc->bus_range = bus_range;
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rc->pcie.bus = bus_range->start;
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err = cdns_pcie_host_init_root_port(rc);
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if (err)
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goto err_out;
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return err;
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err = cdns_pcie_host_init_address_translation(rc);
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if (err)
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goto err_out;
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return 0;
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err_out:
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pci_free_resource_list(resources);
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return err;
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return cdns_pcie_host_init_address_translation(rc);
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}
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static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
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@@ -450,7 +425,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *np = dev->of_node;
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struct pci_host_bridge *bridge;
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struct list_head resources;
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enum cdns_pcie_rp_bar bar;
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struct cdns_pcie *pcie;
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struct resource *res;
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@@ -469,8 +443,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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rc->device_id = 0xffff;
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of_property_read_u32(np, "device-id", &rc->device_id);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
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pcie->reg_base = devm_ioremap_resource(dev, res);
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pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
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if (IS_ERR(pcie->reg_base)) {
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dev_err(dev, "missing \"reg\"\n");
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return PTR_ERR(pcie->reg_base);
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@@ -478,10 +451,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
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rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
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if (IS_ERR(rc->cfg_base)) {
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dev_err(dev, "missing \"cfg\"\n");
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if (IS_ERR(rc->cfg_base))
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return PTR_ERR(rc->cfg_base);
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}
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rc->cfg_res = res;
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ret = cdns_pcie_start_link(pcie);
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@@ -497,26 +468,21 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
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rc->avail_ib_bar[bar] = true;
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ret = cdns_pcie_host_init(dev, &resources, rc);
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ret = cdns_pcie_host_init(dev, rc);
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if (ret)
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return ret;
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list_splice_init(&resources, &bridge->windows);
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bridge->dev.parent = dev;
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bridge->busnr = pcie->bus;
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if (!bridge->ops)
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bridge->ops = &cdns_pcie_host_ops;
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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ret = pci_host_probe(bridge);
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if (ret < 0)
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goto err_host_probe;
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goto err_init;
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return 0;
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err_host_probe:
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pci_free_resource_list(&resources);
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err_init:
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pm_runtime_put_sync(dev);
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return ret;
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}
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@@ -7,7 +7,7 @@
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#include "pcie-cadence.h"
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void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
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void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
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u32 r, bool is_io,
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u64 cpu_addr, u64 pci_addr, size_t size)
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{
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@@ -60,7 +60,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
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/* The device and function numbers are always 0. */
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
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CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
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} else {
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/*
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* Use captured values for bus and device numbers but still
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@@ -84,7 +84,8 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
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}
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void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
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void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
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u8 busnr, u8 fn,
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u32 r, u64 cpu_addr)
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{
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u32 addr0, addr1, desc0, desc1;
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@@ -96,7 +97,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
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if (pcie->is_rc) {
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
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CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
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desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
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} else {
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desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
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}
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@@ -272,7 +272,6 @@ struct cdns_pcie {
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struct resource *mem_res;
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struct device *dev;
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bool is_rc;
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u8 bus;
|
||||
int phy_count;
|
||||
struct phy **phy;
|
||||
struct device_link **link;
|
||||
@@ -285,7 +284,6 @@ struct cdns_pcie {
|
||||
* @dev: pointer to PCIe device
|
||||
* @cfg_res: start/end offsets in the physical system memory to map PCI
|
||||
* configuration space accesses
|
||||
* @bus_range: first/last buses behind the PCIe host controller
|
||||
* @cfg_base: IO mapped window to access the PCI configuration space of a
|
||||
* single function at a time
|
||||
* @vendor_id: PCI vendor ID
|
||||
@@ -296,7 +294,6 @@ struct cdns_pcie {
|
||||
struct cdns_pcie_rc {
|
||||
struct cdns_pcie pcie;
|
||||
struct resource *cfg_res;
|
||||
struct resource *bus_range;
|
||||
void __iomem *cfg_base;
|
||||
u32 vendor_id;
|
||||
u32 device_id;
|
||||
@@ -498,11 +495,12 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
|
||||
void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
|
||||
u32 r, bool is_io,
|
||||
u64 cpu_addr, u64 pci_addr, size_t size);
|
||||
|
||||
void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
|
||||
void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
|
||||
u8 busnr, u8 fn,
|
||||
u32 r, u64 cpu_addr);
|
||||
|
||||
void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
|
||||
|
||||
Reference in New Issue
Block a user