[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -56,27 +56,27 @@
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* Temporary until all gas have MT ASE support
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*/
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.macro DMT reg=0
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.word (0x41600bc1 | (\reg << 16))
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.word 0x41600bc1 | (\reg << 16)
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.endm
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.macro EMT reg=0
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.word (0x41600be1 | (\reg << 16))
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.word 0x41600be1 | (\reg << 16)
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.endm
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.macro DVPE reg=0
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.word (0x41600001 | (\reg << 16))
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.word 0x41600001 | (\reg << 16)
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.endm
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.macro EVPE reg=0
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.word (0x41600021 | (\reg << 16))
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.word 0x41600021 | (\reg << 16)
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.endm
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.macro MFTR rt=0, rd=0, u=0, sel=0
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.word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel))
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.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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.macro MTTR rt=0, rd=0, u=0, sel=0
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.word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel))
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.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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#endif /* _ASM_ASMMACRO_H */
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@@ -19,14 +19,14 @@
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#include <asm/sgidefs.h>
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#include <asm/war.h>
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#if (_MIPS_SZLONG == 32)
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#if _MIPS_SZLONG == 32
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#define SZLONG_LOG 5
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#define SZLONG_MASK 31UL
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#define __LL "ll "
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#define __SC "sc "
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#define __INS "ins "
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#define __EXT "ext "
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#elif (_MIPS_SZLONG == 64)
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#elif _MIPS_SZLONG == 64
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#define SZLONG_LOG 6
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#define SZLONG_MASK 63UL
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#define __LL "lld "
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@@ -461,7 +461,7 @@ static inline int __ilog2(unsigned long x)
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int lz;
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if (sizeof(x) == 4) {
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__asm__ (
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__asm__(
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" .set push \n"
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" .set mips32 \n"
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" clz %0, %1 \n"
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@@ -474,7 +474,7 @@ static inline int __ilog2(unsigned long x)
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BUG_ON(sizeof(x) != 8);
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__asm__ (
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__asm__(
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" .set push \n"
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" .set mips64 \n"
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" dclz %0, %1 \n"
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@@ -508,7 +508,7 @@ static inline unsigned long __ffs(unsigned long word)
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*/
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static inline int fls(int word)
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{
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__asm__ ("clz %0, %1" : "=r" (word) : "r" (word));
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__asm__("clz %0, %1" : "=r" (word) : "r" (word));
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return 32 - word;
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}
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@@ -516,7 +516,7 @@ static inline int fls(int word)
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#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
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static inline int fls64(__u64 word)
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{
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__asm__ ("dclz %0, %1" : "=r" (word) : "r" (word));
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__asm__("dclz %0, %1" : "=r" (word) : "r" (word));
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return 64 - word;
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}
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@@ -65,9 +65,9 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
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#endif /* __GNUC__ */
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#if defined (__MIPSEB__)
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#if defined(__MIPSEB__)
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# include <linux/byteorder/big_endian.h>
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#elif defined (__MIPSEL__)
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#elif defined(__MIPSEL__)
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# include <linux/byteorder/little_endian.h>
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#else
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# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
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@@ -319,7 +319,7 @@ do { \
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struct task_struct;
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extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
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extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
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extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
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extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
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#define ELF_CORE_COPY_REGS(elf_regs, regs) \
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@@ -60,8 +60,8 @@ enum fixed_addresses {
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__end_of_fixed_addresses
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};
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extern void __set_fixmap (enum fixed_addresses idx,
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unsigned long phys, pgprot_t flags);
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extern void __set_fixmap(enum fixed_addresses idx,
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unsigned long phys, pgprot_t flags);
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#define set_fixmap(idx, phys) \
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__set_fixmap(idx, phys, PAGE_KERNEL)
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@@ -75,7 +75,7 @@
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}
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static inline int
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futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
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futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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@@ -17,8 +17,8 @@ typedef struct inventory_s {
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extern int inventory_items;
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extern void add_to_inventory (int class, int type, int controller, int unit, int state);
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extern int dump_inventory_to_user (void __user *userbuf, int size);
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extern void add_to_inventory(int class, int type, int controller, int unit, int state);
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extern int dump_inventory_to_user(void __user *userbuf, int size);
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extern int __init init_inventory(void);
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#endif /* __ASM_INVENTORY_H */
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@@ -16,7 +16,7 @@
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#include <linux/compiler.h>
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#include <asm/hazards.h>
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__asm__ (
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__asm__(
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" .macro raw_local_irq_enable \n"
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" .set push \n"
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" .set reorder \n"
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@@ -65,7 +65,7 @@ static inline void raw_local_irq_enable(void)
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*
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* Workaround: mask EXL bit of the result or place a nop before mfc0.
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*/
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__asm__ (
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__asm__(
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" .macro raw_local_irq_disable\n"
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" .set push \n"
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" .set noat \n"
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@@ -96,7 +96,7 @@ static inline void raw_local_irq_disable(void)
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: "memory");
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}
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__asm__ (
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__asm__(
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" .macro raw_local_save_flags flags \n"
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" .set push \n"
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" .set reorder \n"
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@@ -113,7 +113,7 @@ __asm__ __volatile__( \
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"raw_local_save_flags %0" \
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: "=r" (x))
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__asm__ (
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__asm__(
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" .macro raw_local_irq_save result \n"
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" .set push \n"
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" .set reorder \n"
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@@ -145,7 +145,7 @@ __asm__ __volatile__( \
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: /* no inputs */ \
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: "memory")
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__asm__ (
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__asm__(
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" .macro raw_local_irq_restore flags \n"
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" .set push \n"
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" .set noreorder \n"
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@@ -951,25 +951,25 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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/* Programmable Counters 0 and 1 */
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#define SYS_BASE 0xB1900000
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#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
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#define SYS_CNTRL_E1S (1<<23)
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#define SYS_CNTRL_T1S (1<<20)
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#define SYS_CNTRL_M21 (1<<19)
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#define SYS_CNTRL_M11 (1<<18)
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#define SYS_CNTRL_M01 (1<<17)
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#define SYS_CNTRL_C1S (1<<16)
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#define SYS_CNTRL_BP (1<<14)
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#define SYS_CNTRL_EN1 (1<<13)
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#define SYS_CNTRL_BT1 (1<<12)
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#define SYS_CNTRL_EN0 (1<<11)
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#define SYS_CNTRL_BT0 (1<<10)
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#define SYS_CNTRL_E0 (1<<8)
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#define SYS_CNTRL_E0S (1<<7)
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#define SYS_CNTRL_32S (1<<5)
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#define SYS_CNTRL_T0S (1<<4)
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#define SYS_CNTRL_M20 (1<<3)
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#define SYS_CNTRL_M10 (1<<2)
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#define SYS_CNTRL_M00 (1<<1)
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#define SYS_CNTRL_C0S (1<<0)
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# define SYS_CNTRL_E1S (1<<23)
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# define SYS_CNTRL_T1S (1<<20)
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# define SYS_CNTRL_M21 (1<<19)
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# define SYS_CNTRL_M11 (1<<18)
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# define SYS_CNTRL_M01 (1<<17)
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# define SYS_CNTRL_C1S (1<<16)
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# define SYS_CNTRL_BP (1<<14)
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# define SYS_CNTRL_EN1 (1<<13)
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# define SYS_CNTRL_BT1 (1<<12)
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# define SYS_CNTRL_EN0 (1<<11)
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# define SYS_CNTRL_BT0 (1<<10)
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# define SYS_CNTRL_E0 (1<<8)
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# define SYS_CNTRL_E0S (1<<7)
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# define SYS_CNTRL_32S (1<<5)
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# define SYS_CNTRL_T0S (1<<4)
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# define SYS_CNTRL_M20 (1<<3)
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# define SYS_CNTRL_M10 (1<<2)
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# define SYS_CNTRL_M00 (1<<1)
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# define SYS_CNTRL_C0S (1<<0)
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/* Programmable Counter 0 Registers */
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#define SYS_TOYTRIM (SYS_BASE + 0)
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@@ -989,34 +989,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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/* I2S Controller */
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#define I2S_DATA 0xB1000000
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#define I2S_DATA_MASK (0xffffff)
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# define I2S_DATA_MASK (0xffffff)
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#define I2S_CONFIG 0xB1000004
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#define I2S_CONFIG_XU (1<<25)
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#define I2S_CONFIG_XO (1<<24)
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#define I2S_CONFIG_RU (1<<23)
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#define I2S_CONFIG_RO (1<<22)
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#define I2S_CONFIG_TR (1<<21)
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#define I2S_CONFIG_TE (1<<20)
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#define I2S_CONFIG_TF (1<<19)
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#define I2S_CONFIG_RR (1<<18)
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#define I2S_CONFIG_RE (1<<17)
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#define I2S_CONFIG_RF (1<<16)
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#define I2S_CONFIG_PD (1<<11)
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#define I2S_CONFIG_LB (1<<10)
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#define I2S_CONFIG_IC (1<<9)
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#define I2S_CONFIG_FM_BIT 7
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#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
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#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
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#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
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#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
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#define I2S_CONFIG_TN (1<<6)
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#define I2S_CONFIG_RN (1<<5)
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#define I2S_CONFIG_SZ_BIT 0
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#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
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# define I2S_CONFIG_XU (1<<25)
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# define I2S_CONFIG_XO (1<<24)
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# define I2S_CONFIG_RU (1<<23)
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# define I2S_CONFIG_RO (1<<22)
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# define I2S_CONFIG_TR (1<<21)
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# define I2S_CONFIG_TE (1<<20)
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# define I2S_CONFIG_TF (1<<19)
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# define I2S_CONFIG_RR (1<<18)
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# define I2S_CONFIG_RE (1<<17)
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# define I2S_CONFIG_RF (1<<16)
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# define I2S_CONFIG_PD (1<<11)
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# define I2S_CONFIG_LB (1<<10)
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# define I2S_CONFIG_IC (1<<9)
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# define I2S_CONFIG_FM_BIT 7
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# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
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# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
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# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
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# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
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# define I2S_CONFIG_TN (1<<6)
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# define I2S_CONFIG_RN (1<<5)
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# define I2S_CONFIG_SZ_BIT 0
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# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
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#define I2S_CONTROL 0xB1000008
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#define I2S_CONTROL_D (1<<1)
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#define I2S_CONTROL_CE (1<<0)
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# define I2S_CONTROL_D (1<<1)
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# define I2S_CONTROL_CE (1<<0)
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/* USB Host Controller */
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#ifndef USB_OHCI_LEN
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@@ -1034,38 +1034,38 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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#define USBD_EP5RD 0xB0200014
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#define USBD_INTEN 0xB0200018
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#define USBD_INTSTAT 0xB020001C
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#define USBDEV_INT_SOF (1<<12)
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#define USBDEV_INT_HF_BIT 6
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#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
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#define USBDEV_INT_CMPLT_BIT 0
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#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
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# define USBDEV_INT_SOF (1<<12)
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# define USBDEV_INT_HF_BIT 6
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# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
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# define USBDEV_INT_CMPLT_BIT 0
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# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
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#define USBD_CONFIG 0xB0200020
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#define USBD_EP0CS 0xB0200024
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#define USBD_EP2CS 0xB0200028
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#define USBD_EP3CS 0xB020002C
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#define USBD_EP4CS 0xB0200030
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#define USBD_EP5CS 0xB0200034
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#define USBDEV_CS_SU (1<<14)
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#define USBDEV_CS_NAK (1<<13)
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#define USBDEV_CS_ACK (1<<12)
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#define USBDEV_CS_BUSY (1<<11)
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#define USBDEV_CS_TSIZE_BIT 1
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#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
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#define USBDEV_CS_STALL (1<<0)
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# define USBDEV_CS_SU (1<<14)
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# define USBDEV_CS_NAK (1<<13)
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# define USBDEV_CS_ACK (1<<12)
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# define USBDEV_CS_BUSY (1<<11)
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# define USBDEV_CS_TSIZE_BIT 1
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# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
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# define USBDEV_CS_STALL (1<<0)
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#define USBD_EP0RDSTAT 0xB0200040
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#define USBD_EP0WRSTAT 0xB0200044
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#define USBD_EP2WRSTAT 0xB0200048
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#define USBD_EP3WRSTAT 0xB020004C
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#define USBD_EP4RDSTAT 0xB0200050
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#define USBD_EP5RDSTAT 0xB0200054
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#define USBDEV_FSTAT_FLUSH (1<<6)
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#define USBDEV_FSTAT_UF (1<<5)
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#define USBDEV_FSTAT_OF (1<<4)
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#define USBDEV_FSTAT_FCNT_BIT 0
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#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
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# define USBDEV_FSTAT_FLUSH (1<<6)
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# define USBDEV_FSTAT_UF (1<<5)
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# define USBDEV_FSTAT_OF (1<<4)
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# define USBDEV_FSTAT_FCNT_BIT 0
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# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
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#define USBD_ENABLE 0xB0200058
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#define USBDEV_ENABLE (1<<1)
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#define USBDEV_CE (1<<0)
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# define USBDEV_ENABLE (1<<1)
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# define USBDEV_CE (1<<0)
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#endif /* !CONFIG_SOC_AU1200 */
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@@ -1073,55 +1073,55 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
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/* 4 byte offsets from AU1000_ETH_BASE */
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#define MAC_CONTROL 0x0
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#define MAC_RX_ENABLE (1<<2)
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#define MAC_TX_ENABLE (1<<3)
|
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#define MAC_DEF_CHECK (1<<5)
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#define MAC_SET_BL(X) (((X)&0x3)<<6)
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#define MAC_AUTO_PAD (1<<8)
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#define MAC_DISABLE_RETRY (1<<10)
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#define MAC_DISABLE_BCAST (1<<11)
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#define MAC_LATE_COL (1<<12)
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#define MAC_HASH_MODE (1<<13)
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#define MAC_HASH_ONLY (1<<15)
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#define MAC_PASS_ALL (1<<16)
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#define MAC_INVERSE_FILTER (1<<17)
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#define MAC_PROMISCUOUS (1<<18)
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#define MAC_PASS_ALL_MULTI (1<<19)
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#define MAC_FULL_DUPLEX (1<<20)
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#define MAC_NORMAL_MODE 0
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#define MAC_INT_LOOPBACK (1<<21)
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#define MAC_EXT_LOOPBACK (1<<22)
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#define MAC_DISABLE_RX_OWN (1<<23)
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#define MAC_BIG_ENDIAN (1<<30)
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#define MAC_RX_ALL (1<<31)
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# define MAC_RX_ENABLE (1<<2)
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# define MAC_TX_ENABLE (1<<3)
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# define MAC_DEF_CHECK (1<<5)
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# define MAC_SET_BL(X) (((X)&0x3)<<6)
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# define MAC_AUTO_PAD (1<<8)
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# define MAC_DISABLE_RETRY (1<<10)
|
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# define MAC_DISABLE_BCAST (1<<11)
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# define MAC_LATE_COL (1<<12)
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# define MAC_HASH_MODE (1<<13)
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# define MAC_HASH_ONLY (1<<15)
|
||||
# define MAC_PASS_ALL (1<<16)
|
||||
# define MAC_INVERSE_FILTER (1<<17)
|
||||
# define MAC_PROMISCUOUS (1<<18)
|
||||
# define MAC_PASS_ALL_MULTI (1<<19)
|
||||
# define MAC_FULL_DUPLEX (1<<20)
|
||||
# define MAC_NORMAL_MODE 0
|
||||
# define MAC_INT_LOOPBACK (1<<21)
|
||||
# define MAC_EXT_LOOPBACK (1<<22)
|
||||
# define MAC_DISABLE_RX_OWN (1<<23)
|
||||
# define MAC_BIG_ENDIAN (1<<30)
|
||||
# define MAC_RX_ALL (1<<31)
|
||||
#define MAC_ADDRESS_HIGH 0x4
|
||||
#define MAC_ADDRESS_LOW 0x8
|
||||
#define MAC_MCAST_HIGH 0xC
|
||||
#define MAC_MCAST_LOW 0x10
|
||||
#define MAC_MII_CNTRL 0x14
|
||||
#define MAC_MII_BUSY (1<<0)
|
||||
#define MAC_MII_READ 0
|
||||
#define MAC_MII_WRITE (1<<1)
|
||||
#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
|
||||
#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
|
||||
# define MAC_MII_BUSY (1<<0)
|
||||
# define MAC_MII_READ 0
|
||||
# define MAC_MII_WRITE (1<<1)
|
||||
# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
|
||||
# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
|
||||
#define MAC_MII_DATA 0x18
|
||||
#define MAC_FLOW_CNTRL 0x1C
|
||||
#define MAC_FLOW_CNTRL_BUSY (1<<0)
|
||||
#define MAC_FLOW_CNTRL_ENABLE (1<<1)
|
||||
#define MAC_PASS_CONTROL (1<<2)
|
||||
#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
|
||||
# define MAC_FLOW_CNTRL_BUSY (1<<0)
|
||||
# define MAC_FLOW_CNTRL_ENABLE (1<<1)
|
||||
# define MAC_PASS_CONTROL (1<<2)
|
||||
# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
|
||||
#define MAC_VLAN1_TAG 0x20
|
||||
#define MAC_VLAN2_TAG 0x24
|
||||
|
||||
/* Ethernet Controller Enable */
|
||||
|
||||
#define MAC_EN_CLOCK_ENABLE (1<<0)
|
||||
#define MAC_EN_RESET0 (1<<1)
|
||||
#define MAC_EN_TOSS (0<<2)
|
||||
#define MAC_EN_CACHEABLE (1<<3)
|
||||
#define MAC_EN_RESET1 (1<<4)
|
||||
#define MAC_EN_RESET2 (1<<5)
|
||||
#define MAC_DMA_RESET (1<<6)
|
||||
# define MAC_EN_CLOCK_ENABLE (1<<0)
|
||||
# define MAC_EN_RESET0 (1<<1)
|
||||
# define MAC_EN_TOSS (0<<2)
|
||||
# define MAC_EN_CACHEABLE (1<<3)
|
||||
# define MAC_EN_RESET1 (1<<4)
|
||||
# define MAC_EN_RESET2 (1<<5)
|
||||
# define MAC_DMA_RESET (1<<6)
|
||||
|
||||
/* Ethernet Controller DMA Channels */
|
||||
|
||||
@@ -1129,22 +1129,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
#define MAC1_TX_DMA_ADDR 0xB4004200
|
||||
/* offsets from MAC_TX_RING_ADDR address */
|
||||
#define MAC_TX_BUFF0_STATUS 0x0
|
||||
#define TX_FRAME_ABORTED (1<<0)
|
||||
#define TX_JAB_TIMEOUT (1<<1)
|
||||
#define TX_NO_CARRIER (1<<2)
|
||||
#define TX_LOSS_CARRIER (1<<3)
|
||||
#define TX_EXC_DEF (1<<4)
|
||||
#define TX_LATE_COLL_ABORT (1<<5)
|
||||
#define TX_EXC_COLL (1<<6)
|
||||
#define TX_UNDERRUN (1<<7)
|
||||
#define TX_DEFERRED (1<<8)
|
||||
#define TX_LATE_COLL (1<<9)
|
||||
#define TX_COLL_CNT_MASK (0xF<<10)
|
||||
#define TX_PKT_RETRY (1<<31)
|
||||
# define TX_FRAME_ABORTED (1<<0)
|
||||
# define TX_JAB_TIMEOUT (1<<1)
|
||||
# define TX_NO_CARRIER (1<<2)
|
||||
# define TX_LOSS_CARRIER (1<<3)
|
||||
# define TX_EXC_DEF (1<<4)
|
||||
# define TX_LATE_COLL_ABORT (1<<5)
|
||||
# define TX_EXC_COLL (1<<6)
|
||||
# define TX_UNDERRUN (1<<7)
|
||||
# define TX_DEFERRED (1<<8)
|
||||
# define TX_LATE_COLL (1<<9)
|
||||
# define TX_COLL_CNT_MASK (0xF<<10)
|
||||
# define TX_PKT_RETRY (1<<31)
|
||||
#define MAC_TX_BUFF0_ADDR 0x4
|
||||
#define TX_DMA_ENABLE (1<<0)
|
||||
#define TX_T_DONE (1<<1)
|
||||
#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
|
||||
# define TX_DMA_ENABLE (1<<0)
|
||||
# define TX_T_DONE (1<<1)
|
||||
# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
|
||||
#define MAC_TX_BUFF0_LEN 0x8
|
||||
#define MAC_TX_BUFF1_STATUS 0x10
|
||||
#define MAC_TX_BUFF1_ADDR 0x14
|
||||
@@ -1160,34 +1160,34 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
#define MAC1_RX_DMA_ADDR 0xB4004300
|
||||
/* offsets from MAC_RX_RING_ADDR */
|
||||
#define MAC_RX_BUFF0_STATUS 0x0
|
||||
#define RX_FRAME_LEN_MASK 0x3fff
|
||||
#define RX_WDOG_TIMER (1<<14)
|
||||
#define RX_RUNT (1<<15)
|
||||
#define RX_OVERLEN (1<<16)
|
||||
#define RX_COLL (1<<17)
|
||||
#define RX_ETHER (1<<18)
|
||||
#define RX_MII_ERROR (1<<19)
|
||||
#define RX_DRIBBLING (1<<20)
|
||||
#define RX_CRC_ERROR (1<<21)
|
||||
#define RX_VLAN1 (1<<22)
|
||||
#define RX_VLAN2 (1<<23)
|
||||
#define RX_LEN_ERROR (1<<24)
|
||||
#define RX_CNTRL_FRAME (1<<25)
|
||||
#define RX_U_CNTRL_FRAME (1<<26)
|
||||
#define RX_MCAST_FRAME (1<<27)
|
||||
#define RX_BCAST_FRAME (1<<28)
|
||||
#define RX_FILTER_FAIL (1<<29)
|
||||
#define RX_PACKET_FILTER (1<<30)
|
||||
#define RX_MISSED_FRAME (1<<31)
|
||||
# define RX_FRAME_LEN_MASK 0x3fff
|
||||
# define RX_WDOG_TIMER (1<<14)
|
||||
# define RX_RUNT (1<<15)
|
||||
# define RX_OVERLEN (1<<16)
|
||||
# define RX_COLL (1<<17)
|
||||
# define RX_ETHER (1<<18)
|
||||
# define RX_MII_ERROR (1<<19)
|
||||
# define RX_DRIBBLING (1<<20)
|
||||
# define RX_CRC_ERROR (1<<21)
|
||||
# define RX_VLAN1 (1<<22)
|
||||
# define RX_VLAN2 (1<<23)
|
||||
# define RX_LEN_ERROR (1<<24)
|
||||
# define RX_CNTRL_FRAME (1<<25)
|
||||
# define RX_U_CNTRL_FRAME (1<<26)
|
||||
# define RX_MCAST_FRAME (1<<27)
|
||||
# define RX_BCAST_FRAME (1<<28)
|
||||
# define RX_FILTER_FAIL (1<<29)
|
||||
# define RX_PACKET_FILTER (1<<30)
|
||||
# define RX_MISSED_FRAME (1<<31)
|
||||
|
||||
#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
|
||||
# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
|
||||
RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
|
||||
RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
|
||||
#define MAC_RX_BUFF0_ADDR 0x4
|
||||
#define RX_DMA_ENABLE (1<<0)
|
||||
#define RX_T_DONE (1<<1)
|
||||
#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
|
||||
#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
|
||||
# define RX_DMA_ENABLE (1<<0)
|
||||
# define RX_T_DONE (1<<1)
|
||||
# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
|
||||
# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
|
||||
#define MAC_RX_BUFF1_STATUS 0x10
|
||||
#define MAC_RX_BUFF1_ADDR 0x14
|
||||
#define MAC_RX_BUFF2_STATUS 0x20
|
||||
@@ -1298,44 +1298,44 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
|
||||
/* SSIO */
|
||||
#define SSI0_STATUS 0xB1600000
|
||||
#define SSI_STATUS_BF (1<<4)
|
||||
#define SSI_STATUS_OF (1<<3)
|
||||
#define SSI_STATUS_UF (1<<2)
|
||||
#define SSI_STATUS_D (1<<1)
|
||||
#define SSI_STATUS_B (1<<0)
|
||||
# define SSI_STATUS_BF (1<<4)
|
||||
# define SSI_STATUS_OF (1<<3)
|
||||
# define SSI_STATUS_UF (1<<2)
|
||||
# define SSI_STATUS_D (1<<1)
|
||||
# define SSI_STATUS_B (1<<0)
|
||||
#define SSI0_INT 0xB1600004
|
||||
#define SSI_INT_OI (1<<3)
|
||||
#define SSI_INT_UI (1<<2)
|
||||
#define SSI_INT_DI (1<<1)
|
||||
# define SSI_INT_OI (1<<3)
|
||||
# define SSI_INT_UI (1<<2)
|
||||
# define SSI_INT_DI (1<<1)
|
||||
#define SSI0_INT_ENABLE 0xB1600008
|
||||
#define SSI_INTE_OIE (1<<3)
|
||||
#define SSI_INTE_UIE (1<<2)
|
||||
#define SSI_INTE_DIE (1<<1)
|
||||
# define SSI_INTE_OIE (1<<3)
|
||||
# define SSI_INTE_UIE (1<<2)
|
||||
# define SSI_INTE_DIE (1<<1)
|
||||
#define SSI0_CONFIG 0xB1600020
|
||||
#define SSI_CONFIG_AO (1<<24)
|
||||
#define SSI_CONFIG_DO (1<<23)
|
||||
#define SSI_CONFIG_ALEN_BIT 20
|
||||
#define SSI_CONFIG_ALEN_MASK (0x7<<20)
|
||||
#define SSI_CONFIG_DLEN_BIT 16
|
||||
#define SSI_CONFIG_DLEN_MASK (0x7<<16)
|
||||
#define SSI_CONFIG_DD (1<<11)
|
||||
#define SSI_CONFIG_AD (1<<10)
|
||||
#define SSI_CONFIG_BM_BIT 8
|
||||
#define SSI_CONFIG_BM_MASK (0x3<<8)
|
||||
#define SSI_CONFIG_CE (1<<7)
|
||||
#define SSI_CONFIG_DP (1<<6)
|
||||
#define SSI_CONFIG_DL (1<<5)
|
||||
#define SSI_CONFIG_EP (1<<4)
|
||||
# define SSI_CONFIG_AO (1<<24)
|
||||
# define SSI_CONFIG_DO (1<<23)
|
||||
# define SSI_CONFIG_ALEN_BIT 20
|
||||
# define SSI_CONFIG_ALEN_MASK (0x7<<20)
|
||||
# define SSI_CONFIG_DLEN_BIT 16
|
||||
# define SSI_CONFIG_DLEN_MASK (0x7<<16)
|
||||
# define SSI_CONFIG_DD (1<<11)
|
||||
# define SSI_CONFIG_AD (1<<10)
|
||||
# define SSI_CONFIG_BM_BIT 8
|
||||
# define SSI_CONFIG_BM_MASK (0x3<<8)
|
||||
# define SSI_CONFIG_CE (1<<7)
|
||||
# define SSI_CONFIG_DP (1<<6)
|
||||
# define SSI_CONFIG_DL (1<<5)
|
||||
# define SSI_CONFIG_EP (1<<4)
|
||||
#define SSI0_ADATA 0xB1600024
|
||||
#define SSI_AD_D (1<<24)
|
||||
#define SSI_AD_ADDR_BIT 16
|
||||
#define SSI_AD_ADDR_MASK (0xff<<16)
|
||||
#define SSI_AD_DATA_BIT 0
|
||||
#define SSI_AD_DATA_MASK (0xfff<<0)
|
||||
# define SSI_AD_D (1<<24)
|
||||
# define SSI_AD_ADDR_BIT 16
|
||||
# define SSI_AD_ADDR_MASK (0xff<<16)
|
||||
# define SSI_AD_DATA_BIT 0
|
||||
# define SSI_AD_DATA_MASK (0xfff<<0)
|
||||
#define SSI0_CLKDIV 0xB1600028
|
||||
#define SSI0_CONTROL 0xB1600100
|
||||
#define SSI_CONTROL_CD (1<<1)
|
||||
#define SSI_CONTROL_E (1<<0)
|
||||
# define SSI_CONTROL_CD (1<<1)
|
||||
# define SSI_CONTROL_E (1<<0)
|
||||
|
||||
/* SSI1 */
|
||||
#define SSI1_STATUS 0xB1680000
|
||||
@@ -1401,75 +1401,75 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
|
||||
#define IR_INT_CLEAR (IRDA_BASE+0x18)
|
||||
#define IR_CONFIG_1 (IRDA_BASE+0x20)
|
||||
#define IR_RX_INVERT_LED (1<<0)
|
||||
#define IR_TX_INVERT_LED (1<<1)
|
||||
#define IR_ST (1<<2)
|
||||
#define IR_SF (1<<3)
|
||||
#define IR_SIR (1<<4)
|
||||
#define IR_MIR (1<<5)
|
||||
#define IR_FIR (1<<6)
|
||||
#define IR_16CRC (1<<7)
|
||||
#define IR_TD (1<<8)
|
||||
#define IR_RX_ALL (1<<9)
|
||||
#define IR_DMA_ENABLE (1<<10)
|
||||
#define IR_RX_ENABLE (1<<11)
|
||||
#define IR_TX_ENABLE (1<<12)
|
||||
#define IR_LOOPBACK (1<<14)
|
||||
#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
|
||||
# define IR_RX_INVERT_LED (1<<0)
|
||||
# define IR_TX_INVERT_LED (1<<1)
|
||||
# define IR_ST (1<<2)
|
||||
# define IR_SF (1<<3)
|
||||
# define IR_SIR (1<<4)
|
||||
# define IR_MIR (1<<5)
|
||||
# define IR_FIR (1<<6)
|
||||
# define IR_16CRC (1<<7)
|
||||
# define IR_TD (1<<8)
|
||||
# define IR_RX_ALL (1<<9)
|
||||
# define IR_DMA_ENABLE (1<<10)
|
||||
# define IR_RX_ENABLE (1<<11)
|
||||
# define IR_TX_ENABLE (1<<12)
|
||||
# define IR_LOOPBACK (1<<14)
|
||||
# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
|
||||
IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
|
||||
#define IR_SIR_FLAGS (IRDA_BASE+0x24)
|
||||
#define IR_ENABLE (IRDA_BASE+0x28)
|
||||
#define IR_RX_STATUS (1<<9)
|
||||
#define IR_TX_STATUS (1<<10)
|
||||
# define IR_RX_STATUS (1<<9)
|
||||
# define IR_TX_STATUS (1<<10)
|
||||
#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
|
||||
#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
|
||||
#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
|
||||
#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
|
||||
#define IR_CONFIG_2 (IRDA_BASE+0x3C)
|
||||
#define IR_MODE_INV (1<<0)
|
||||
#define IR_ONE_PIN (1<<1)
|
||||
# define IR_MODE_INV (1<<0)
|
||||
# define IR_ONE_PIN (1<<1)
|
||||
#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
|
||||
|
||||
/* GPIO */
|
||||
#define SYS_PINFUNC 0xB190002C
|
||||
#define SYS_PF_USB (1<<15) /* 2nd USB device/host */
|
||||
#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
|
||||
#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
|
||||
#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
|
||||
#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
|
||||
#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
|
||||
#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
|
||||
#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
|
||||
#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
|
||||
#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
|
||||
#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
|
||||
#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
|
||||
#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
|
||||
#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
|
||||
#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
|
||||
#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
|
||||
# define SYS_PF_USB (1<<15) /* 2nd USB device/host */
|
||||
# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
|
||||
# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
|
||||
# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
|
||||
# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
|
||||
# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
|
||||
# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
|
||||
# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
|
||||
# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
|
||||
# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
|
||||
# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
|
||||
# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
|
||||
# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
|
||||
# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
|
||||
# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
|
||||
# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
|
||||
|
||||
/* Au1100 Only */
|
||||
#define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
|
||||
#define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
|
||||
#define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
|
||||
#define SYS_PF_EX0 (1<<9) /* gpio2/clock */
|
||||
# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
|
||||
# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
|
||||
# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
|
||||
# define SYS_PF_EX0 (1<<9) /* gpio2/clock */
|
||||
|
||||
/* Au1550 Only. Redefines lots of pins */
|
||||
#define SYS_PF_PSC2_MASK (7 << 17)
|
||||
#define SYS_PF_PSC2_AC97 (0)
|
||||
#define SYS_PF_PSC2_SPI (0)
|
||||
#define SYS_PF_PSC2_I2S (1 << 17)
|
||||
#define SYS_PF_PSC2_SMBUS (3 << 17)
|
||||
#define SYS_PF_PSC2_GPIO (7 << 17)
|
||||
#define SYS_PF_PSC3_MASK (7 << 20)
|
||||
#define SYS_PF_PSC3_AC97 (0)
|
||||
#define SYS_PF_PSC3_SPI (0)
|
||||
#define SYS_PF_PSC3_I2S (1 << 20)
|
||||
#define SYS_PF_PSC3_SMBUS (3 << 20)
|
||||
#define SYS_PF_PSC3_GPIO (7 << 20)
|
||||
#define SYS_PF_PSC1_S1 (1 << 1)
|
||||
#define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
|
||||
# define SYS_PF_PSC2_MASK (7 << 17)
|
||||
# define SYS_PF_PSC2_AC97 (0)
|
||||
# define SYS_PF_PSC2_SPI (0)
|
||||
# define SYS_PF_PSC2_I2S (1 << 17)
|
||||
# define SYS_PF_PSC2_SMBUS (3 << 17)
|
||||
# define SYS_PF_PSC2_GPIO (7 << 17)
|
||||
# define SYS_PF_PSC3_MASK (7 << 20)
|
||||
# define SYS_PF_PSC3_AC97 (0)
|
||||
# define SYS_PF_PSC3_SPI (0)
|
||||
# define SYS_PF_PSC3_I2S (1 << 20)
|
||||
# define SYS_PF_PSC3_SMBUS (3 << 20)
|
||||
# define SYS_PF_PSC3_GPIO (7 << 20)
|
||||
# define SYS_PF_PSC1_S1 (1 << 1)
|
||||
# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
|
||||
|
||||
/* Au1200 Only */
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
@@ -1530,104 +1530,104 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
|
||||
/* Clock Controller */
|
||||
#define SYS_FREQCTRL0 0xB1900020
|
||||
#define SYS_FC_FRDIV2_BIT 22
|
||||
#define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
|
||||
#define SYS_FC_FE2 (1<<21)
|
||||
#define SYS_FC_FS2 (1<<20)
|
||||
#define SYS_FC_FRDIV1_BIT 12
|
||||
#define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
|
||||
#define SYS_FC_FE1 (1<<11)
|
||||
#define SYS_FC_FS1 (1<<10)
|
||||
#define SYS_FC_FRDIV0_BIT 2
|
||||
#define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
|
||||
#define SYS_FC_FE0 (1<<1)
|
||||
#define SYS_FC_FS0 (1<<0)
|
||||
# define SYS_FC_FRDIV2_BIT 22
|
||||
# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
|
||||
# define SYS_FC_FE2 (1<<21)
|
||||
# define SYS_FC_FS2 (1<<20)
|
||||
# define SYS_FC_FRDIV1_BIT 12
|
||||
# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
|
||||
# define SYS_FC_FE1 (1<<11)
|
||||
# define SYS_FC_FS1 (1<<10)
|
||||
# define SYS_FC_FRDIV0_BIT 2
|
||||
# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
|
||||
# define SYS_FC_FE0 (1<<1)
|
||||
# define SYS_FC_FS0 (1<<0)
|
||||
#define SYS_FREQCTRL1 0xB1900024
|
||||
#define SYS_FC_FRDIV5_BIT 22
|
||||
#define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
|
||||
#define SYS_FC_FE5 (1<<21)
|
||||
#define SYS_FC_FS5 (1<<20)
|
||||
#define SYS_FC_FRDIV4_BIT 12
|
||||
#define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
|
||||
#define SYS_FC_FE4 (1<<11)
|
||||
#define SYS_FC_FS4 (1<<10)
|
||||
#define SYS_FC_FRDIV3_BIT 2
|
||||
#define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
|
||||
#define SYS_FC_FE3 (1<<1)
|
||||
#define SYS_FC_FS3 (1<<0)
|
||||
# define SYS_FC_FRDIV5_BIT 22
|
||||
# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
|
||||
# define SYS_FC_FE5 (1<<21)
|
||||
# define SYS_FC_FS5 (1<<20)
|
||||
# define SYS_FC_FRDIV4_BIT 12
|
||||
# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
|
||||
# define SYS_FC_FE4 (1<<11)
|
||||
# define SYS_FC_FS4 (1<<10)
|
||||
# define SYS_FC_FRDIV3_BIT 2
|
||||
# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
|
||||
# define SYS_FC_FE3 (1<<1)
|
||||
# define SYS_FC_FS3 (1<<0)
|
||||
#define SYS_CLKSRC 0xB1900028
|
||||
#define SYS_CS_ME1_BIT 27
|
||||
#define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
|
||||
#define SYS_CS_DE1 (1<<26)
|
||||
#define SYS_CS_CE1 (1<<25)
|
||||
#define SYS_CS_ME0_BIT 22
|
||||
#define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
|
||||
#define SYS_CS_DE0 (1<<21)
|
||||
#define SYS_CS_CE0 (1<<20)
|
||||
#define SYS_CS_MI2_BIT 17
|
||||
#define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
|
||||
#define SYS_CS_DI2 (1<<16)
|
||||
#define SYS_CS_CI2 (1<<15)
|
||||
# define SYS_CS_ME1_BIT 27
|
||||
# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
|
||||
# define SYS_CS_DE1 (1<<26)
|
||||
# define SYS_CS_CE1 (1<<25)
|
||||
# define SYS_CS_ME0_BIT 22
|
||||
# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
|
||||
# define SYS_CS_DE0 (1<<21)
|
||||
# define SYS_CS_CE0 (1<<20)
|
||||
# define SYS_CS_MI2_BIT 17
|
||||
# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
|
||||
# define SYS_CS_DI2 (1<<16)
|
||||
# define SYS_CS_CI2 (1<<15)
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
#define SYS_CS_ML_BIT 7
|
||||
#define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
|
||||
#define SYS_CS_DL (1<<6)
|
||||
#define SYS_CS_CL (1<<5)
|
||||
# define SYS_CS_ML_BIT 7
|
||||
# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
|
||||
# define SYS_CS_DL (1<<6)
|
||||
# define SYS_CS_CL (1<<5)
|
||||
#else
|
||||
#define SYS_CS_MUH_BIT 12
|
||||
#define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
|
||||
#define SYS_CS_DUH (1<<11)
|
||||
#define SYS_CS_CUH (1<<10)
|
||||
#define SYS_CS_MUD_BIT 7
|
||||
#define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
|
||||
#define SYS_CS_DUD (1<<6)
|
||||
#define SYS_CS_CUD (1<<5)
|
||||
# define SYS_CS_MUH_BIT 12
|
||||
# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
|
||||
# define SYS_CS_DUH (1<<11)
|
||||
# define SYS_CS_CUH (1<<10)
|
||||
# define SYS_CS_MUD_BIT 7
|
||||
# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
|
||||
# define SYS_CS_DUD (1<<6)
|
||||
# define SYS_CS_CUD (1<<5)
|
||||
#endif
|
||||
#define SYS_CS_MIR_BIT 2
|
||||
#define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
|
||||
#define SYS_CS_DIR (1<<1)
|
||||
#define SYS_CS_CIR (1<<0)
|
||||
# define SYS_CS_MIR_BIT 2
|
||||
# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
|
||||
# define SYS_CS_DIR (1<<1)
|
||||
# define SYS_CS_CIR (1<<0)
|
||||
|
||||
#define SYS_CS_MUX_AUX 0x1
|
||||
#define SYS_CS_MUX_FQ0 0x2
|
||||
#define SYS_CS_MUX_FQ1 0x3
|
||||
#define SYS_CS_MUX_FQ2 0x4
|
||||
#define SYS_CS_MUX_FQ3 0x5
|
||||
#define SYS_CS_MUX_FQ4 0x6
|
||||
#define SYS_CS_MUX_FQ5 0x7
|
||||
# define SYS_CS_MUX_AUX 0x1
|
||||
# define SYS_CS_MUX_FQ0 0x2
|
||||
# define SYS_CS_MUX_FQ1 0x3
|
||||
# define SYS_CS_MUX_FQ2 0x4
|
||||
# define SYS_CS_MUX_FQ3 0x5
|
||||
# define SYS_CS_MUX_FQ4 0x6
|
||||
# define SYS_CS_MUX_FQ5 0x7
|
||||
#define SYS_CPUPLL 0xB1900060
|
||||
#define SYS_AUXPLL 0xB1900064
|
||||
|
||||
/* AC97 Controller */
|
||||
#define AC97C_CONFIG 0xB0000000
|
||||
#define AC97C_RECV_SLOTS_BIT 13
|
||||
#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
|
||||
#define AC97C_XMIT_SLOTS_BIT 3
|
||||
#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
|
||||
#define AC97C_SG (1<<2)
|
||||
#define AC97C_SYNC (1<<1)
|
||||
#define AC97C_RESET (1<<0)
|
||||
# define AC97C_RECV_SLOTS_BIT 13
|
||||
# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
|
||||
# define AC97C_XMIT_SLOTS_BIT 3
|
||||
# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
|
||||
# define AC97C_SG (1<<2)
|
||||
# define AC97C_SYNC (1<<1)
|
||||
# define AC97C_RESET (1<<0)
|
||||
#define AC97C_STATUS 0xB0000004
|
||||
#define AC97C_XU (1<<11)
|
||||
#define AC97C_XO (1<<10)
|
||||
#define AC97C_RU (1<<9)
|
||||
#define AC97C_RO (1<<8)
|
||||
#define AC97C_READY (1<<7)
|
||||
#define AC97C_CP (1<<6)
|
||||
#define AC97C_TR (1<<5)
|
||||
#define AC97C_TE (1<<4)
|
||||
#define AC97C_TF (1<<3)
|
||||
#define AC97C_RR (1<<2)
|
||||
#define AC97C_RE (1<<1)
|
||||
#define AC97C_RF (1<<0)
|
||||
# define AC97C_XU (1<<11)
|
||||
# define AC97C_XO (1<<10)
|
||||
# define AC97C_RU (1<<9)
|
||||
# define AC97C_RO (1<<8)
|
||||
# define AC97C_READY (1<<7)
|
||||
# define AC97C_CP (1<<6)
|
||||
# define AC97C_TR (1<<5)
|
||||
# define AC97C_TE (1<<4)
|
||||
# define AC97C_TF (1<<3)
|
||||
# define AC97C_RR (1<<2)
|
||||
# define AC97C_RE (1<<1)
|
||||
# define AC97C_RF (1<<0)
|
||||
#define AC97C_DATA 0xB0000008
|
||||
#define AC97C_CMD 0xB000000C
|
||||
#define AC97C_WD_BIT 16
|
||||
#define AC97C_READ (1<<7)
|
||||
#define AC97C_INDEX_MASK 0x7f
|
||||
# define AC97C_WD_BIT 16
|
||||
# define AC97C_READ (1<<7)
|
||||
# define AC97C_INDEX_MASK 0x7f
|
||||
#define AC97C_CNTRL 0xB0000010
|
||||
#define AC97C_RS (1<<1)
|
||||
#define AC97C_CE (1<<0)
|
||||
# define AC97C_RS (1<<1)
|
||||
# define AC97C_CE (1<<0)
|
||||
|
||||
|
||||
/* Secure Digital (SD) Controller */
|
||||
@@ -1636,12 +1636,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
||||
#define SD1_XMIT_FIFO 0xB0680000
|
||||
#define SD1_RECV_FIFO 0xB0680004
|
||||
|
||||
#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
|
||||
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
|
||||
/* Au1500 PCI Controller */
|
||||
#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
|
||||
#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
|
||||
#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
|
||||
#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
|
||||
# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
|
||||
#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
|
||||
#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
|
||||
#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
|
||||
|
||||
@@ -136,7 +136,7 @@ void auide_outl(u32 addr, unsigned long port);
|
||||
void auide_outsw(unsigned long port, void *addr, u32 count);
|
||||
void auide_outsl(unsigned long port, void *addr, u32 count);
|
||||
static void auide_tune_drive(ide_drive_t *drive, byte pio);
|
||||
static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
|
||||
static int auide_tune_chipset(ide_drive_t *drive, u8 speed);
|
||||
static int auide_ddma_init( _auide_hwif *auide );
|
||||
static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
|
||||
int __init auide_probe(void);
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
#define __ASM_MACH_IP32_KMALLOC_H
|
||||
|
||||
|
||||
#if defined(CONFIG_CPU_R5000) || defined (CONFIG_CPU_RM7000)
|
||||
#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
|
||||
#define ARCH_KMALLOC_MINALIGN 32
|
||||
#else
|
||||
#define ARCH_KMALLOC_MINALIGN 128
|
||||
|
||||
@@ -32,38 +32,38 @@
|
||||
#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
|
||||
|
||||
#define PB1000_PCR 0xBE000000
|
||||
#define PCR_SLOT_0_VPP0 (1<<0)
|
||||
#define PCR_SLOT_0_VPP1 (1<<1)
|
||||
#define PCR_SLOT_0_VCC0 (1<<2)
|
||||
#define PCR_SLOT_0_VCC1 (1<<3)
|
||||
#define PCR_SLOT_0_RST (1<<4)
|
||||
# define PCR_SLOT_0_VPP0 (1<<0)
|
||||
# define PCR_SLOT_0_VPP1 (1<<1)
|
||||
# define PCR_SLOT_0_VCC0 (1<<2)
|
||||
# define PCR_SLOT_0_VCC1 (1<<3)
|
||||
# define PCR_SLOT_0_RST (1<<4)
|
||||
|
||||
#define PCR_SLOT_1_VPP0 (1<<8)
|
||||
#define PCR_SLOT_1_VPP1 (1<<9)
|
||||
#define PCR_SLOT_1_VCC0 (1<<10)
|
||||
#define PCR_SLOT_1_VCC1 (1<<11)
|
||||
#define PCR_SLOT_1_RST (1<<12)
|
||||
# define PCR_SLOT_1_VPP0 (1<<8)
|
||||
# define PCR_SLOT_1_VPP1 (1<<9)
|
||||
# define PCR_SLOT_1_VCC0 (1<<10)
|
||||
# define PCR_SLOT_1_VCC1 (1<<11)
|
||||
# define PCR_SLOT_1_RST (1<<12)
|
||||
|
||||
#define PB1000_MDR 0xBE000004
|
||||
#define MDR_PI (1<<5) /* pcmcia int latch */
|
||||
#define MDR_EPI (1<<14) /* enable pcmcia int */
|
||||
#define MDR_CPI (1<<15) /* clear pcmcia int */
|
||||
# define MDR_PI (1<<5) /* pcmcia int latch */
|
||||
# define MDR_EPI (1<<14) /* enable pcmcia int */
|
||||
# define MDR_CPI (1<<15) /* clear pcmcia int */
|
||||
|
||||
#define PB1000_ACR1 0xBE000008
|
||||
#define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
|
||||
#define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
|
||||
#define ACR1_SLOT_0_READY (1<<2) /* ready */
|
||||
#define ACR1_SLOT_0_STATUS (1<<3) /* status change */
|
||||
#define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
|
||||
#define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
|
||||
#define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
|
||||
#define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
|
||||
#define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
|
||||
#define ACR1_SLOT_1_READY (1<<10) /* ready */
|
||||
#define ACR1_SLOT_1_STATUS (1<<11) /* status change */
|
||||
#define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
|
||||
#define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
|
||||
#define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
|
||||
# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
|
||||
# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
|
||||
# define ACR1_SLOT_0_READY (1<<2) /* ready */
|
||||
# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
|
||||
# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
|
||||
# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
|
||||
# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
|
||||
# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
|
||||
# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
|
||||
# define ACR1_SLOT_1_READY (1<<10) /* ready */
|
||||
# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
|
||||
# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
|
||||
# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
|
||||
# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
|
||||
|
||||
#define CPLD_AUX0 0xBE00000C
|
||||
#define CPLD_AUX1 0xBE000010
|
||||
|
||||
@@ -29,44 +29,44 @@
|
||||
|
||||
#define PB1100_IDENT 0xAE000000
|
||||
#define BOARD_STATUS_REG 0xAE000004
|
||||
#define PB1100_ROM_SEL (1<<15)
|
||||
#define PB1100_ROM_SIZ (1<<14)
|
||||
#define PB1100_SWAP_BOOT (1<<13)
|
||||
#define PB1100_FLASH_WP (1<<12)
|
||||
#define PB1100_ROM_H_STS (1<<11)
|
||||
#define PB1100_ROM_L_STS (1<<10)
|
||||
#define PB1100_FLASH_H_STS (1<<9)
|
||||
#define PB1100_FLASH_L_STS (1<<8)
|
||||
#define PB1100_SRAM_SIZ (1<<7)
|
||||
#define PB1100_TSC_BUSY (1<<6)
|
||||
#define PB1100_PCMCIA_VS_MASK (3<<4)
|
||||
#define PB1100_RS232_CD (1<<3)
|
||||
#define PB1100_RS232_CTS (1<<2)
|
||||
#define PB1100_RS232_DSR (1<<1)
|
||||
#define PB1100_RS232_RI (1<<0)
|
||||
# define PB1100_ROM_SEL (1<<15)
|
||||
# define PB1100_ROM_SIZ (1<<14)
|
||||
# define PB1100_SWAP_BOOT (1<<13)
|
||||
# define PB1100_FLASH_WP (1<<12)
|
||||
# define PB1100_ROM_H_STS (1<<11)
|
||||
# define PB1100_ROM_L_STS (1<<10)
|
||||
# define PB1100_FLASH_H_STS (1<<9)
|
||||
# define PB1100_FLASH_L_STS (1<<8)
|
||||
# define PB1100_SRAM_SIZ (1<<7)
|
||||
# define PB1100_TSC_BUSY (1<<6)
|
||||
# define PB1100_PCMCIA_VS_MASK (3<<4)
|
||||
# define PB1100_RS232_CD (1<<3)
|
||||
# define PB1100_RS232_CTS (1<<2)
|
||||
# define PB1100_RS232_DSR (1<<1)
|
||||
# define PB1100_RS232_RI (1<<0)
|
||||
|
||||
#define PB1100_IRDA_RS232 0xAE00000C
|
||||
#define PB1100_IRDA_FULL (0<<14) /* full power */
|
||||
#define PB1100_IRDA_SHUTDOWN (1<<14)
|
||||
#define PB1100_IRDA_TT (2<<14) /* 2/3 power */
|
||||
#define PB1100_IRDA_OT (3<<14) /* 1/3 power */
|
||||
#define PB1100_IRDA_FIR (1<<13)
|
||||
# define PB1100_IRDA_FULL (0<<14) /* full power */
|
||||
# define PB1100_IRDA_SHUTDOWN (1<<14)
|
||||
# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
|
||||
# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
|
||||
# define PB1100_IRDA_FIR (1<<13)
|
||||
|
||||
#define PCMCIA_BOARD_REG 0xAE000010
|
||||
#define PB1100_SD_WP1_RO (1<<15) /* read only */
|
||||
#define PB1100_SD_WP0_RO (1<<14) /* read only */
|
||||
#define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
|
||||
#define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
|
||||
#define PB1100_SEL_SD_CONN1 (1<<9)
|
||||
#define PB1100_SEL_SD_CONN0 (1<<8)
|
||||
#define PC_DEASSERT_RST (1<<7)
|
||||
#define PC_DRV_EN (1<<4)
|
||||
# define PB1100_SD_WP1_RO (1<<15) /* read only */
|
||||
# define PB1100_SD_WP0_RO (1<<14) /* read only */
|
||||
# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
|
||||
# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
|
||||
# define PB1100_SEL_SD_CONN1 (1<<9)
|
||||
# define PB1100_SEL_SD_CONN0 (1<<8)
|
||||
# define PC_DEASSERT_RST (1<<7)
|
||||
# define PC_DRV_EN (1<<4)
|
||||
|
||||
#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
|
||||
|
||||
#define PB1100_RST_VDDI 0xAE00001C
|
||||
#define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
|
||||
#define PB1100_VDDI_MASK (0x1F)
|
||||
# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
|
||||
# define PB1100_VDDI_MASK (0x1F)
|
||||
|
||||
#define PB1100_LEDS 0xAE000018
|
||||
|
||||
|
||||
@@ -200,10 +200,10 @@ pr4450_instr_cache_invalidated:
|
||||
|
||||
icache_invd_loop:
|
||||
/* 9 == register t1 */
|
||||
.word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(0 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY0 */
|
||||
.word (CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(1 * ICACHE_SET_SIZE)) /* invalidate inst cache WAY1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
|
||||
(1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
|
||||
|
||||
addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
|
||||
bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
|
||||
@@ -235,14 +235,14 @@ pr4450_instr_cache_invalidated:
|
||||
|
||||
dcache_wbinvd_loop:
|
||||
/* 9 == register t1 */
|
||||
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(0 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY0 */
|
||||
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(1 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY1 */
|
||||
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(2 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY2 */
|
||||
.word (CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(3 * DCACHE_SET_SIZE)) /* writeback/invalidate WAY3 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
|
||||
.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
|
||||
(3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
|
||||
|
||||
addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
|
||||
bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
|
||||
|
||||
@@ -6,10 +6,10 @@
|
||||
#ifndef _ASM_PARPORT_H
|
||||
#define _ASM_PARPORT_H
|
||||
|
||||
static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
|
||||
static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
|
||||
static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
|
||||
static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
|
||||
{
|
||||
return parport_pc_find_isa_ports (autoirq, autodma);
|
||||
return parport_pc_find_isa_ports(autoirq, autodma);
|
||||
}
|
||||
|
||||
#endif /* _ASM_PARPORT_H */
|
||||
|
||||
@@ -36,6 +36,6 @@ struct prda {
|
||||
|
||||
#define t_sys prda_sys
|
||||
|
||||
ptrdiff_t prctl (int op, int v1, int v2);
|
||||
ptrdiff_t prctl(int op, int v1, int v2);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -51,18 +51,18 @@ struct semaphore {
|
||||
#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
|
||||
#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
|
||||
|
||||
static inline void sema_init (struct semaphore *sem, int val)
|
||||
static inline void sema_init(struct semaphore *sem, int val)
|
||||
{
|
||||
atomic_set(&sem->count, val);
|
||||
init_waitqueue_head(&sem->wait);
|
||||
}
|
||||
|
||||
static inline void init_MUTEX (struct semaphore *sem)
|
||||
static inline void init_MUTEX(struct semaphore *sem)
|
||||
{
|
||||
sema_init(sem, 1);
|
||||
}
|
||||
|
||||
static inline void init_MUTEX_LOCKED (struct semaphore *sem)
|
||||
static inline void init_MUTEX_LOCKED(struct semaphore *sem)
|
||||
{
|
||||
sema_init(sem, 0);
|
||||
}
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
#ifdef CONFIG_32BIT
|
||||
|
||||
#define save_static_function(symbol) \
|
||||
__asm__ ( \
|
||||
__asm__( \
|
||||
".text\n\t" \
|
||||
".globl\t" #symbol "\n\t" \
|
||||
".align\t2\n\t" \
|
||||
@@ -46,7 +46,7 @@ __asm__ ( \
|
||||
#ifdef CONFIG_64BIT
|
||||
|
||||
#define save_static_function(symbol) \
|
||||
__asm__ ( \
|
||||
__asm__( \
|
||||
".text\n\t" \
|
||||
".globl\t" #symbol "\n\t" \
|
||||
".align\t2\n\t" \
|
||||
|
||||
@@ -50,7 +50,7 @@
|
||||
#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
|
||||
|
||||
#define CHANGE_ADDR_NASID(_pa, _nasid) \
|
||||
((UINT64_CAST (_pa) & ~NASID_MASK) | \
|
||||
((UINT64_CAST(_pa) & ~NASID_MASK) | \
|
||||
(UINT64_CAST(_nasid) << NASID_SHFT))
|
||||
|
||||
|
||||
@@ -75,7 +75,7 @@
|
||||
|
||||
|
||||
#define RAW_NODE_SWIN_BASE(nasid, widget) \
|
||||
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
|
||||
(NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
|
||||
|
||||
#define WIDGETID_GET(addr) ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
|
||||
|
||||
@@ -192,21 +192,21 @@
|
||||
#define BDDIR_ENTRY_LO(_pa) ((HSPEC_BASE + \
|
||||
NODE_ADDRSPACE_SIZE * 3 / 4 + \
|
||||
0x200) | \
|
||||
UINT64_CAST (_pa) & NASID_MASK | \
|
||||
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
|
||||
UINT64_CAST (_pa) >> 3 & 0x1f << 4)
|
||||
UINT64_CAST(_pa) & NASID_MASK | \
|
||||
UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
|
||||
UINT64_CAST(_pa) >> 3 & 0x1f << 4)
|
||||
|
||||
#define BDDIR_ENTRY_HI(_pa) ((HSPEC_BASE + \
|
||||
NODE_ADDRSPACE_SIZE * 3 / 4 + \
|
||||
0x208) | \
|
||||
UINT64_CAST (_pa) & NASID_MASK | \
|
||||
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
|
||||
UINT64_CAST (_pa) >> 3 & 0x1f << 4)
|
||||
UINT64_CAST(_pa) & NASID_MASK | \
|
||||
UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
|
||||
UINT64_CAST(_pa) >> 3 & 0x1f << 4)
|
||||
|
||||
#define BDPRT_ENTRY(_pa, _rgn) ((HSPEC_BASE + \
|
||||
NODE_ADDRSPACE_SIZE * 3 / 4) | \
|
||||
UINT64_CAST (_pa) & NASID_MASK | \
|
||||
UINT64_CAST (_pa) >> 2 & BDDIR_UPPER_MASK | \
|
||||
UINT64_CAST(_pa) & NASID_MASK | \
|
||||
UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK | \
|
||||
(_rgn) << 3)
|
||||
#define BDPRT_ENTRY_ADDR(_pa,_rgn) (BDPRT_ENTRY((_pa),(_rgn)))
|
||||
#define BDPRT_ENTRY_S(_pa,_rgn,_val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa),(_rgn))=(_val))
|
||||
@@ -214,9 +214,9 @@
|
||||
|
||||
#define BDECC_ENTRY(_pa) ((HSPEC_BASE + \
|
||||
NODE_ADDRSPACE_SIZE / 2) | \
|
||||
UINT64_CAST (_pa) & NASID_MASK | \
|
||||
UINT64_CAST (_pa) >> 2 & BDECC_UPPER_MASK | \
|
||||
UINT64_CAST (_pa) >> 3 & 3)
|
||||
UINT64_CAST(_pa) & NASID_MASK | \
|
||||
UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK | \
|
||||
UINT64_CAST(_pa) >> 3 & 3)
|
||||
|
||||
/*
|
||||
* Macro to convert a back door directory or protection address into the
|
||||
@@ -225,16 +225,16 @@
|
||||
#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x200) != 0)
|
||||
#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x200) == 0)
|
||||
|
||||
#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
|
||||
(UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2 | \
|
||||
(UINT64_CAST (_ba) & 0x1f << 4) << 3)
|
||||
#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
|
||||
(UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2 | \
|
||||
(UINT64_CAST(_ba) & 0x1f << 4) << 3)
|
||||
|
||||
#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
|
||||
(UINT64_CAST (_ba) & BDDIR_UPPER_MASK)<<2)
|
||||
#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
|
||||
(UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
|
||||
|
||||
#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
|
||||
(UINT64_CAST (_ba) & BDECC_UPPER_MASK)<<2 | \
|
||||
(UINT64_CAST (_ba) & 3) << 3)
|
||||
#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \
|
||||
(UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2 | \
|
||||
(UINT64_CAST(_ba) & 3) << 3)
|
||||
#endif /* CONFIG_SGI_IP27 */
|
||||
|
||||
|
||||
@@ -282,7 +282,7 @@
|
||||
* the base of the register space.
|
||||
*/
|
||||
#define HUB_REG_PTR(_base, _off) \
|
||||
(HUBREG_CAST ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
|
||||
(HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
|
||||
|
||||
#define HUB_REG_PTR_L(_base, _off) \
|
||||
HUB_L(HUB_REG_PTR((_base), (_off)))
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
#ifndef _ASM_SN_IO_H
|
||||
#define _ASM_SN_IO_H
|
||||
|
||||
#if defined (CONFIG_SGI_IP27)
|
||||
#if defined(CONFIG_SGI_IP27)
|
||||
#include <asm/sn/sn0/hubio.h>
|
||||
#endif
|
||||
|
||||
|
||||
@@ -140,7 +140,7 @@
|
||||
*/
|
||||
#define SYMMON_STACK_SIZE 0x8000
|
||||
|
||||
#if defined (PROM)
|
||||
#if defined(PROM)
|
||||
|
||||
/*
|
||||
* These defines are prom version dependent. No code other than the IP27
|
||||
|
||||
@@ -91,7 +91,7 @@
|
||||
: RAW_NODE_SWIN_BASE(nasid, widget))
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define NODE_SWIN_BASE(nasid, widget) \
|
||||
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
|
||||
(NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
@@ -106,7 +106,7 @@
|
||||
#define BWIN_WIDGET_MASK 0x7
|
||||
#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
|
||||
#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
|
||||
(UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
|
||||
(UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
|
||||
|
||||
#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
|
||||
#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
|
||||
@@ -259,7 +259,7 @@
|
||||
* CACHE_ERR_SP_PTR could either contain an address to the stack, or
|
||||
* the stack could start at CACHE_ERR_SP_PTR
|
||||
*/
|
||||
#if defined (HUB_ERR_STS_WAR)
|
||||
#if defined(HUB_ERR_STS_WAR)
|
||||
#define CACHE_ERR_EFRAME 0x480
|
||||
#else /* HUB_ERR_STS_WAR */
|
||||
#define CACHE_ERR_EFRAME 0x400
|
||||
@@ -275,7 +275,7 @@
|
||||
|
||||
#define _ARCSPROM
|
||||
|
||||
#if defined (HUB_ERR_STS_WAR)
|
||||
#if defined(HUB_ERR_STS_WAR)
|
||||
|
||||
#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
|
||||
#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
|
||||
|
||||
@@ -194,17 +194,17 @@ extern unsigned int sni_brd_type;
|
||||
#define PCIMT_INT_ACKNOWLEDGE 0xba000000
|
||||
|
||||
/* board specific init functions */
|
||||
extern void sni_a20r_init (void);
|
||||
extern void sni_pcit_init (void);
|
||||
extern void sni_rm200_init (void);
|
||||
extern void sni_pcimt_init (void);
|
||||
extern void sni_a20r_init(void);
|
||||
extern void sni_pcit_init(void);
|
||||
extern void sni_rm200_init(void);
|
||||
extern void sni_pcimt_init(void);
|
||||
|
||||
/* board specific irq init functions */
|
||||
extern void sni_a20r_irq_init (void);
|
||||
extern void sni_pcit_irq_init (void);
|
||||
extern void sni_pcit_cplus_irq_init (void);
|
||||
extern void sni_rm200_irq_init (void);
|
||||
extern void sni_pcimt_irq_init (void);
|
||||
extern void sni_a20r_irq_init(void);
|
||||
extern void sni_pcit_irq_init(void);
|
||||
extern void sni_pcit_cplus_irq_init(void);
|
||||
extern void sni_rm200_irq_init(void);
|
||||
extern void sni_pcimt_irq_init(void);
|
||||
|
||||
/* timer inits */
|
||||
extern void sni_cpu_time_init(void);
|
||||
|
||||
@@ -195,11 +195,11 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
|
||||
|
||||
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
|
||||
|
||||
extern void set_handler (unsigned long offset, void *addr, unsigned long len);
|
||||
extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
|
||||
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
|
||||
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
|
||||
|
||||
typedef void (*vi_handler_t)(void);
|
||||
extern void *set_vi_handler (int n, vi_handler_t addr);
|
||||
extern void *set_vi_handler(int n, vi_handler_t addr);
|
||||
|
||||
extern void *set_except_vector(int n, void *addr);
|
||||
extern unsigned long ebase;
|
||||
|
||||
@@ -48,7 +48,7 @@
|
||||
|
||||
typedef unsigned int cycles_t;
|
||||
|
||||
static inline cycles_t get_cycles (void)
|
||||
static inline cycles_t get_cycles(void)
|
||||
{
|
||||
return read_c0_count();
|
||||
}
|
||||
|
||||
@@ -391,9 +391,9 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
|
||||
|
||||
#define __invoke_copy_to_user(to,from,n) \
|
||||
({ \
|
||||
register void __user *__cu_to_r __asm__ ("$4"); \
|
||||
register const void *__cu_from_r __asm__ ("$5"); \
|
||||
register long __cu_len_r __asm__ ("$6"); \
|
||||
register void __user *__cu_to_r __asm__("$4"); \
|
||||
register const void *__cu_from_r __asm__("$5"); \
|
||||
register long __cu_len_r __asm__("$6"); \
|
||||
\
|
||||
__cu_to_r = (to); \
|
||||
__cu_from_r = (from); \
|
||||
@@ -495,9 +495,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
|
||||
|
||||
#define __invoke_copy_from_user(to,from,n) \
|
||||
({ \
|
||||
register void *__cu_to_r __asm__ ("$4"); \
|
||||
register const void __user *__cu_from_r __asm__ ("$5"); \
|
||||
register long __cu_len_r __asm__ ("$6"); \
|
||||
register void *__cu_to_r __asm__("$4"); \
|
||||
register const void __user *__cu_from_r __asm__("$5"); \
|
||||
register long __cu_len_r __asm__("$6"); \
|
||||
\
|
||||
__cu_to_r = (to); \
|
||||
__cu_from_r = (from); \
|
||||
@@ -518,9 +518,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
|
||||
|
||||
#define __invoke_copy_from_user_inatomic(to,from,n) \
|
||||
({ \
|
||||
register void *__cu_to_r __asm__ ("$4"); \
|
||||
register const void __user *__cu_from_r __asm__ ("$5"); \
|
||||
register long __cu_len_r __asm__ ("$6"); \
|
||||
register void *__cu_to_r __asm__("$4"); \
|
||||
register const void __user *__cu_from_r __asm__("$5"); \
|
||||
register long __cu_len_r __asm__("$6"); \
|
||||
\
|
||||
__cu_to_r = (to); \
|
||||
__cu_from_r = (from); \
|
||||
|
||||
Reference in New Issue
Block a user