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Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm

Bläddra i källkod 
Pull drm updates from Dave Airlie:
 "Core:
   - shared fencing staging removal
   - drop transactional atomic helpers and move helpers to new location
   - DP/MST atomic cleanup
   - Leasing cleanups and drop EXPORT_SYMBOL
   - Convert drivers to atomic helpers and generic fbdev.
   - removed deprecated obj_ref/unref in favour of get/put
   - Improve dumb callback documentation
   - MODESET_LOCK_BEGIN/END helpers

  panels:
   - CDTech panels, Banana Pi Panel, DLC1010GIG,
   - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA,
   - Himax HX8357D, simulated RTSM AEMv8.
   - GPD Win2 panel
   - AUO G101EVN010

  vgem:
   - render node support

  ttm:
   - move global init out of drivers
   - fix LRU handling for ghost objects
   - Support for simultaneous submissions to multiple engines

  scheduler:
   - timeout/fault handling changes to help GPU recovery
   - helpers for hw with preemption support

  i915:
   - Scaler/Watermark fixes
   - DP MST + powerwell fixes
   - PSR fixes
   - Break long get/put shmemfs pages
   - Icelake fixes
   - Icelake DSI video mode enablement
   - Engine workaround improvements

  amdgpu:
   - freesync support
   - GPU reset enabled on CI, VI, SOC15 dGPUs
   - ABM support in DC
   - KFD support for vega12/polaris12
   - SDMA paging queue on vega
   - More amdkfd code sharing
   - DCC scanout on GFX9
   - DC kerneldoc
   - Updated SMU firmware for GFX8 chips
   - XGMI PSP + hive reset support
   - GPU reset
   - DC trace support
   - Powerplay updates for newer Polaris
   - Cursor plane update fast path
   - kfd dma-buf support

  virtio-gpu:
   - add EDID support

  vmwgfx:
   - pageflip with damage support

  nouveau:
   - Initial Turing TU104/TU106 modesetting support

  msm:
   - a2xx gpu support for apq8060 and imx5
   - a2xx gpummu support
   - mdp4 display support for apq8060
   - DPU fixes and cleanups
   - enhanced profiling support
   - debug object naming interface
   - get_iova/page pinning decoupling

  tegra:
   - Tegra194 host1x, VIC and display support enabled
   - Audio over HDMI for Tegra186 and Tegra194

  exynos:
   - DMA/IOMMU refactoring
   - plane alpha + blend mode support
   - Color format fixes for mixer driver

  rcar-du:
   - R8A7744 and R8A77470 support
   - R8A77965 LVDS support

  imx:
   - fbdev emulation fix
   - multi-tiled scalling fixes
   - SPDX identifiers

  rockchip
   - dw_hdmi support
   - dw-mipi-dsi + dual dsi support
   - mailbox read size fix

  qxl:
   - fix cursor pinning

  vc4:
   - YUV support (scaling + cursor)

  v3d:
   - enable TFU (Texture Formatting Unit)

  mali-dp:
   - add support for linear tiled formats

  sun4i:
   - Display Engine 3 support
   - H6 DE3 mixer 0 support
   - H6 display engine support
   - dw-hdmi support
   - H6 HDMI phy support
   - implicit fence waiting
   - BGRX8888 support

  meson:
   - Overlay plane support
   - implicit fence waiting
   - HDMI 1.4 4k modes

  bridge:
   - i2c fixes for sii902x"

* tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits)
  drm/amd/display: Add fast path for cursor plane updates
  drm/amdgpu: Enable GPU recovery by default for CI
  drm/amd/display: Fix duplicating scaling/underscan connector state
  drm/amd/display: Fix unintialized max_bpc state values
  Revert "drm/amd/display: Set RMX_ASPECT as default"
  drm/amdgpu: Fix stub function name
  drm/msm/dpu: Fix clock issue after bind failure
  drm/msm/dpu: Clean up dpu_media_info.h static inline functions
  drm/msm/dpu: Further cleanups for static inline functions
  drm/msm/dpu: Cleanup the debugfs functions
  drm/msm/dpu: Remove dpu_irq and unused functions
  drm/msm: Make irq_postinstall optional
  drm/msm/dpu: Cleanup callers of dpu_hw_blk_init
  drm/msm/dpu: Remove unused functions
  drm/msm/dpu: Remove dpu_crtc_is_enabled()
  drm/msm/dpu: Remove dpu_crtc_get_mixer_height
  drm/msm/dpu: Remove dpu_dbg
  drm/msm: dpu: Remove crtc_lock
  drm/msm: dpu: Remove vblank_requested flag from dpu_crtc
  drm/msm: dpu: Separate crtc assignment from vblank enable
  ...
This commit is contained in:
Linus Torvalds
2018-12-25 11:48:26 -08:00
förälder c76cd634eb 2a3c83f5fe
incheckning 4971f090aa
1030 ändrade filer med 47149 tillägg och 26578 borttagningar
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/meson/Kconfig
Visa fil

@@ -7,6 +7,7 @@ config DRM_MESON
select DRM_GEM_CMA_HELPER
select VIDEOMODE_HELPERS
select REGMAP_MMIO
select MESON_CANVAS
config DRM_MESON_DW_HDMI
tristate "HDMI Synopsys Controller support for Amlogic Meson Display"

2
drivers/gpu/drm/meson/Makefile
Visa fil

@@ -1,5 +1,5 @@
meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o
meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_canvas.o
meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_canvas.o meson_overlay.o
obj-$(CONFIG_DRM_MESON) += meson-drm.o
obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o

7
drivers/gpu/drm/meson/meson_canvas.c
Visa fil

@@ -39,6 +39,7 @@
#define CANVAS_WIDTH_HBIT 0
#define CANVAS_HEIGHT_BIT 9
#define CANVAS_BLKMODE_BIT 24
#define CANVAS_ENDIAN_BIT 26
#define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */
#define CANVAS_LUT_WR_EN (0x2 << 8)
#define CANVAS_LUT_RD_EN (0x1 << 8)
@@ -47,7 +48,8 @@ void meson_canvas_setup(struct meson_drm *priv,
uint32_t canvas_index, uint32_t addr,
uint32_t stride, uint32_t height,
unsigned int wrap,
unsigned int blkmode)
unsigned int blkmode,
unsigned int endian)
{
unsigned int val;
@@ -60,7 +62,8 @@ void meson_canvas_setup(struct meson_drm *priv,
CANVAS_WIDTH_HBIT) |
(height << CANVAS_HEIGHT_BIT) |
(wrap << 22) |
(blkmode << CANVAS_BLKMODE_BIT));
(blkmode << CANVAS_BLKMODE_BIT) |
(endian << CANVAS_ENDIAN_BIT));
regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,
CANVAS_LUT_WR_EN | canvas_index);

11
drivers/gpu/drm/meson/meson_canvas.h
Visa fil

@@ -23,6 +23,9 @@
#define __MESON_CANVAS_H
#define MESON_CANVAS_ID_OSD1 0x4e
#define MESON_CANVAS_ID_VD1_0 0x60
#define MESON_CANVAS_ID_VD1_1 0x61
#define MESON_CANVAS_ID_VD1_2 0x62
/* Canvas configuration. */
#define MESON_CANVAS_WRAP_NONE 0x00
@@ -33,10 +36,16 @@
#define MESON_CANVAS_BLKMODE_32x32 0x01
#define MESON_CANVAS_BLKMODE_64x64 0x02
#define MESON_CANVAS_ENDIAN_SWAP16 0x1
#define MESON_CANVAS_ENDIAN_SWAP32 0x3
#define MESON_CANVAS_ENDIAN_SWAP64 0x7
#define MESON_CANVAS_ENDIAN_SWAP128 0xf
void meson_canvas_setup(struct meson_drm *priv,
uint32_t canvas_index, uint32_t addr,
uint32_t stride, uint32_t height,
unsigned int wrap,
unsigned int blkmode);
unsigned int blkmode,
unsigned int endian);
#endif /* __MESON_CANVAS_H */

263
drivers/gpu/drm/meson/meson_crtc.c
Visa fil

@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/bitfield.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -98,6 +99,10 @@ static void meson_crtc_enable(struct drm_crtc *crtc)
writel(crtc_state->mode.hdisplay,
priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
/* VD1 Preblend vertical start/end */
writel(FIELD_PREP(GENMASK(11, 0), 2303),
priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
priv->io_base + _REG(VPP_MISC));
@@ -126,13 +131,19 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
struct meson_crtc *meson_crtc = to_meson_crtc(crtc);
struct meson_drm *priv = meson_crtc->priv;
DRM_DEBUG_DRIVER("\n");
drm_crtc_vblank_off(crtc);
priv->viu.osd1_enabled = false;
priv->viu.osd1_commit = false;
priv->viu.vd1_enabled = false;
priv->viu.vd1_commit = false;
/* Disable VPP Postblend */
writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND |
VPP_VD1_PREBLEND | VPP_POSTBLEND_ENABLE, 0,
priv->io_base + _REG(VPP_MISC));
if (crtc->state->event && !crtc->state->active) {
@@ -172,6 +183,7 @@ static void meson_crtc_atomic_flush(struct drm_crtc *crtc,
struct meson_drm *priv = meson_crtc->priv;
priv->viu.osd1_commit = true;
priv->viu.vd1_commit = true;
}
static const struct drm_crtc_helper_funcs meson_crtc_helper_funcs = {
@@ -200,26 +212,37 @@ void meson_crtc_irq(struct meson_drm *priv)
priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
writel_relaxed(priv->viu.osd1_blk0_cfg[4],
priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
writel_relaxed(priv->viu.osd_sc_ctrl0,
priv->io_base + _REG(VPP_OSD_SC_CTRL0));
writel_relaxed(priv->viu.osd_sc_i_wh_m1,
priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
writel_relaxed(priv->viu.osd_sc_o_h_start_end,
priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
writel_relaxed(priv->viu.osd_sc_o_v_start_end,
priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
writel_relaxed(priv->viu.osd_sc_v_ini_phase,
priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
writel_relaxed(priv->viu.osd_sc_v_phase_step,
priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
writel_relaxed(priv->viu.osd_sc_h_ini_phase,
priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE));
writel_relaxed(priv->viu.osd_sc_h_phase_step,
priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP));
writel_relaxed(priv->viu.osd_sc_h_ctrl0,
priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
writel_relaxed(priv->viu.osd_sc_v_ctrl0,
priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
/* If output is interlace, make use of the Scaler */
if (priv->viu.osd1_interlace) {
struct drm_plane *plane = priv->primary_plane;
struct drm_plane_state *state = plane->state;
struct drm_rect dest = {
.x1 = state->crtc_x,
.y1 = state->crtc_y,
.x2 = state->crtc_x + state->crtc_w,
.y2 = state->crtc_y + state->crtc_h,
};
meson_vpp_setup_interlace_vscaler_osd1(priv, &dest);
} else
meson_vpp_disable_interlace_vscaler_osd1(priv);
meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
priv->viu.osd1_addr, priv->viu.osd1_stride,
priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR);
if (priv->canvas)
meson_canvas_config(priv->canvas, priv->canvas_id_osd1,
priv->viu.osd1_addr, priv->viu.osd1_stride,
priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR, 0);
else
meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
priv->viu.osd1_addr, priv->viu.osd1_stride,
priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR, 0);
/* Enable OSD1 */
writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
@@ -228,6 +251,206 @@ void meson_crtc_irq(struct meson_drm *priv)
priv->viu.osd1_commit = false;
}
/* Update the VD1 registers */
if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
switch (priv->viu.vd1_planes) {
case 3:
if (priv->canvas)
meson_canvas_config(priv->canvas,
priv->canvas_id_vd1_2,
priv->viu.vd1_addr2,
priv->viu.vd1_stride2,
priv->viu.vd1_height2,
MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR,
MESON_CANVAS_ENDIAN_SWAP64);
else
meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_2,
priv->viu.vd1_addr2,
priv->viu.vd1_stride2,
priv->viu.vd1_height2,
MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR,
MESON_CANVAS_ENDIAN_SWAP64);
/* fallthrough */
case 2:
if (priv->canvas)
meson_canvas_config(priv->canvas,
priv->canvas_id_vd1_1,
priv->viu.vd1_addr1,
priv->viu.vd1_stride1,
priv->viu.vd1_height1,
MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR,
MESON_CANVAS_ENDIAN_SWAP64);
else
meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_1,
priv->viu.vd1_addr2,
priv->viu.vd1_stride2,
priv->viu.vd1_height2,
MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR,
MESON_CANVAS_ENDIAN_SWAP64);
/* fallthrough */
case 1:
if (priv->canvas)
meson_canvas_config(priv->canvas,
priv->canvas_id_vd1_0,
priv->viu.vd1_addr0,
priv->viu.vd1_stride0,
priv->viu.vd1_height0,
MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR,
MESON_CANVAS_ENDIAN_SWAP64);
else
meson_canvas_setup(priv, MESON_CANVAS_ID_VD1_0,
priv->viu.vd1_addr2,
priv->viu.vd1_stride2,
priv->viu.vd1_height2,
MESON_CANVAS_WRAP_NONE,
MESON_CANVAS_BLKMODE_LINEAR,
MESON_CANVAS_ENDIAN_SWAP64);
};
writel_relaxed(priv->viu.vd1_if0_gen_reg,
priv->io_base + _REG(VD1_IF0_GEN_REG));
writel_relaxed(priv->viu.vd1_if0_gen_reg,
priv->io_base + _REG(VD2_IF0_GEN_REG));
writel_relaxed(priv->viu.vd1_if0_gen_reg2,
priv->io_base + _REG(VD1_IF0_GEN_REG2));
writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
priv->io_base + _REG(VIU_VD1_FMT_CTRL));
writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
priv->io_base + _REG(VIU_VD2_FMT_CTRL));
writel_relaxed(priv->viu.viu_vd1_fmt_w,
priv->io_base + _REG(VIU_VD1_FMT_W));
writel_relaxed(priv->viu.viu_vd1_fmt_w,
priv->io_base + _REG(VIU_VD2_FMT_W));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD1_IF0_CANVAS0));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD1_IF0_CANVAS1));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD2_IF0_CANVAS0));
writel_relaxed(priv->viu.vd1_if0_canvas0,
priv->io_base + _REG(VD2_IF0_CANVAS1));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD1_IF0_LUMA_X0));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD1_IF0_LUMA_X1));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD2_IF0_LUMA_X0));
writel_relaxed(priv->viu.vd1_if0_luma_x0,
priv->io_base + _REG(VD2_IF0_LUMA_X1));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD1_IF0_LUMA_Y0));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD1_IF0_LUMA_Y1));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD2_IF0_LUMA_Y0));
writel_relaxed(priv->viu.vd1_if0_luma_y0,
priv->io_base + _REG(VD2_IF0_LUMA_Y1));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD1_IF0_CHROMA_X0));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD1_IF0_CHROMA_X1));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD2_IF0_CHROMA_X0));
writel_relaxed(priv->viu.vd1_if0_chroma_x0,
priv->io_base + _REG(VD2_IF0_CHROMA_X1));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD1_IF0_CHROMA_Y0));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD1_IF0_CHROMA_Y1));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD2_IF0_CHROMA_Y0));
writel_relaxed(priv->viu.vd1_if0_chroma_y0,
priv->io_base + _REG(VD2_IF0_CHROMA_Y1));
writel_relaxed(priv->viu.vd1_if0_repeat_loop,
priv->io_base + _REG(VD1_IF0_RPT_LOOP));
writel_relaxed(priv->viu.vd1_if0_repeat_loop,
priv->io_base + _REG(VD2_IF0_RPT_LOOP));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_LUMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_LUMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_LUMA1_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_LUMA1_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_CHROMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_CHROMA0_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD1_IF0_CHROMA1_RPT_PAT));
writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
priv->io_base + _REG(VD2_IF0_CHROMA1_RPT_PAT));
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_LUMA_PSEL));
writel_relaxed(0, priv->io_base + _REG(VD1_IF0_CHROMA_PSEL));
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_LUMA_PSEL));
writel_relaxed(0, priv->io_base + _REG(VD2_IF0_CHROMA_PSEL));
writel_relaxed(priv->viu.vd1_range_map_y,
priv->io_base + _REG(VD1_IF0_RANGE_MAP_Y));
writel_relaxed(priv->viu.vd1_range_map_cb,
priv->io_base + _REG(VD1_IF0_RANGE_MAP_CB));
writel_relaxed(priv->viu.vd1_range_map_cr,
priv->io_base + _REG(VD1_IF0_RANGE_MAP_CR));
writel_relaxed(0x78404,
priv->io_base + _REG(VPP_SC_MISC));
writel_relaxed(priv->viu.vpp_pic_in_height,
priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
writel_relaxed(priv->viu.vpp_hsc_region12_startp,
priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
writel_relaxed(priv->viu.vpp_hsc_region34_startp,
priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
writel_relaxed(priv->viu.vpp_hsc_region4_endp,
priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
writel_relaxed(priv->viu.vpp_line_in_length,
priv->io_base + _REG(VPP_LINE_IN_LENGTH));
writel_relaxed(priv->viu.vpp_preblend_h_size,
priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
writel_relaxed(priv->viu.vpp_vsc_region12_startp,
priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
writel_relaxed(priv->viu.vpp_vsc_region34_startp,
priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
writel_relaxed(priv->viu.vpp_vsc_region4_endp,
priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
writel_relaxed(priv->viu.vpp_vsc_ini_phase,
priv->io_base + _REG(VPP_VSC_INI_PHASE));
writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
/* Enable VD1 */
writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
VPP_COLOR_MNG_ENABLE,
VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND |
VPP_COLOR_MNG_ENABLE,
priv->io_base + _REG(VPP_MISC));
priv->viu.vd1_commit = false;
}
drm_crtc_handle_vblank(priv->crtc);
spin_lock_irqsave(&priv->drm->event_lock, flags);

91
drivers/gpu/drm/meson/meson_drv.c
Visa fil

@@ -41,6 +41,7 @@
#include "meson_drv.h"
#include "meson_plane.h"
#include "meson_overlay.h"
#include "meson_crtc.h"
#include "meson_venc_cvbs.h"
@@ -68,15 +69,7 @@
* - Powering Up HDMI controller and PHY
*/
static void meson_fb_output_poll_changed(struct drm_device *dev)
{
struct meson_drm *priv = dev->dev_private;
drm_fbdev_cma_hotplug_event(priv->fbdev);
}
static const struct drm_mode_config_funcs meson_mode_config_funcs = {
.output_poll_changed = meson_fb_output_poll_changed,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
.fb_create = drm_gem_fb_create,
@@ -216,24 +209,51 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
goto free_drm;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmc");
if (!res) {
ret = -EINVAL;
goto free_drm;
}
/* Simply ioremap since it may be a shared register zone */
regs = devm_ioremap(dev, res->start, resource_size(res));
if (!regs) {
ret = -EADDRNOTAVAIL;
goto free_drm;
}
priv->canvas = meson_canvas_get(dev);
if (!IS_ERR(priv->canvas)) {
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
if (ret)
goto free_drm;
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
if (ret) {
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
goto free_drm;
}
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
if (ret) {
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
goto free_drm;
}
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
if (ret) {
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
goto free_drm;
}
} else {
priv->canvas = NULL;
priv->dmc = devm_regmap_init_mmio(dev, regs,
&meson_regmap_config);
if (IS_ERR(priv->dmc)) {
dev_err(&pdev->dev, "Couldn't create the DMC regmap\n");
ret = PTR_ERR(priv->dmc);
goto free_drm;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmc");
if (!res) {
ret = -EINVAL;
goto free_drm;
}
/* Simply ioremap since it may be a shared register zone */
regs = devm_ioremap(dev, res->start, resource_size(res));
if (!regs) {
ret = -EADDRNOTAVAIL;
goto free_drm;
}
priv->dmc = devm_regmap_init_mmio(dev, regs,
&meson_regmap_config);
if (IS_ERR(priv->dmc)) {
dev_err(&pdev->dev, "Couldn't create the DMC regmap\n");
ret = PTR_ERR(priv->dmc);
goto free_drm;
}
}
priv->vsync_irq = platform_get_irq(pdev, 0);
@@ -272,6 +292,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
if (ret)
goto free_drm;
ret = meson_overlay_create(priv);
if (ret)
goto free_drm;
ret = meson_crtc_create(priv);
if (ret)
goto free_drm;
@@ -282,13 +306,6 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
drm_mode_config_reset(drm);
priv->fbdev = drm_fbdev_cma_init(drm, 32,
drm->mode_config.num_connector);
if (IS_ERR(priv->fbdev)) {
ret = PTR_ERR(priv->fbdev);
goto free_drm;
}
drm_kms_helper_poll_init(drm);
platform_set_drvdata(pdev, priv);
@@ -297,6 +314,8 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
if (ret)
goto free_drm;
drm_fbdev_generic_setup(drm, 32);
return 0;
free_drm:
@@ -315,9 +334,15 @@ static void meson_drv_unbind(struct device *dev)
struct drm_device *drm = dev_get_drvdata(dev);
struct meson_drm *priv = drm->dev_private;
if (priv->canvas) {
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
}
drm_dev_unregister(drm);
drm_kms_helper_poll_fini(drm);
drm_fbdev_cma_fini(priv->fbdev);
drm_mode_config_cleanup(drm);
drm_dev_put(drm);

67
drivers/gpu/drm/meson/meson_drv.h
Visa fil

@@ -22,6 +22,7 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/soc/amlogic/meson-canvas.h>
#include <drm/drmP.h>
struct meson_drm {
@@ -31,10 +32,16 @@ struct meson_drm {
struct regmap *dmc;
int vsync_irq;
struct meson_canvas *canvas;
u8 canvas_id_osd1;
u8 canvas_id_vd1_0;
u8 canvas_id_vd1_1;
u8 canvas_id_vd1_2;
struct drm_device *drm;
struct drm_crtc *crtc;
struct drm_fbdev_cma *fbdev;
struct drm_plane *primary_plane;
struct drm_plane *overlay_plane;
/* Components Data */
struct {
@@ -46,6 +53,64 @@ struct meson_drm {
uint32_t osd1_addr;
uint32_t osd1_stride;
uint32_t osd1_height;
uint32_t osd_sc_ctrl0;
uint32_t osd_sc_i_wh_m1;
uint32_t osd_sc_o_h_start_end;
uint32_t osd_sc_o_v_start_end;
uint32_t osd_sc_v_ini_phase;
uint32_t osd_sc_v_phase_step;
uint32_t osd_sc_h_ini_phase;
uint32_t osd_sc_h_phase_step;
uint32_t osd_sc_h_ctrl0;
uint32_t osd_sc_v_ctrl0;
bool vd1_enabled;
bool vd1_commit;
unsigned int vd1_planes;
uint32_t vd1_if0_gen_reg;
uint32_t vd1_if0_luma_x0;
uint32_t vd1_if0_luma_y0;
uint32_t vd1_if0_chroma_x0;
uint32_t vd1_if0_chroma_y0;
uint32_t vd1_if0_repeat_loop;
uint32_t vd1_if0_luma0_rpt_pat;
uint32_t vd1_if0_chroma0_rpt_pat;
uint32_t vd1_range_map_y;
uint32_t vd1_range_map_cb;
uint32_t vd1_range_map_cr;
uint32_t viu_vd1_fmt_w;
uint32_t vd1_if0_canvas0;
uint32_t vd1_if0_gen_reg2;
uint32_t viu_vd1_fmt_ctrl;
uint32_t vd1_addr0;
uint32_t vd1_addr1;
uint32_t vd1_addr2;
uint32_t vd1_stride0;
uint32_t vd1_stride1;
uint32_t vd1_stride2;
uint32_t vd1_height0;
uint32_t vd1_height1;
uint32_t vd1_height2;
uint32_t vpp_pic_in_height;
uint32_t vpp_postblend_vd1_h_start_end;
uint32_t vpp_postblend_vd1_v_start_end;
uint32_t vpp_hsc_region12_startp;
uint32_t vpp_hsc_region34_startp;
uint32_t vpp_hsc_region4_endp;
uint32_t vpp_hsc_start_phase_step;
uint32_t vpp_hsc_region1_phase_slope;
uint32_t vpp_hsc_region3_phase_slope;
uint32_t vpp_line_in_length;
uint32_t vpp_preblend_h_size;
uint32_t vpp_vsc_region12_startp;
uint32_t vpp_vsc_region34_startp;
uint32_t vpp_vsc_region4_endp;
uint32_t vpp_vsc_start_phase_step;
uint32_t vpp_vsc_ini_phase;
uint32_t vpp_vsc_phase_ctrl;
uint32_t vpp_hsc_phase_ctrl;
uint32_t vpp_blend_vd2_h_start_end;
uint32_t vpp_blend_vd2_v_start_end;
} viu;
struct {

12
drivers/gpu/drm/meson/meson_dw_hdmi.c
Visa fil

@@ -594,17 +594,7 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
dev_dbg(connector->dev->dev, "%s: vclk:%d venc=%d hdmi=%d\n", __func__,
vclk_freq, venc_freq, hdmi_freq);
/* Finally filter by configurable vclk frequencies for VIC modes */
switch (vclk_freq) {
case 54000:
case 74250:
case 148500:
case 297000:
case 594000:
return MODE_OK;
}
return MODE_CLOCK_RANGE;
return meson_vclk_vic_supported_freq(vclk_freq);
}
/* Encoder */

588
drivers/gpu/drm/meson/meson_overlay.c Normal file
Visa fil

@@ -0,0 +1,588 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/bitfield.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_rect.h>
#include "meson_overlay.h"
#include "meson_vpp.h"
#include "meson_viu.h"
#include "meson_canvas.h"
#include "meson_registers.h"
/* VD1_IF0_GEN_REG */
#define VD_URGENT_CHROMA BIT(28)
#define VD_URGENT_LUMA BIT(27)
#define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)
#define VD_DEMUX_MODE_RGB BIT(16)
#define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)
#define VD_CHRO_RPT_LASTL_CTRL BIT(6)
#define VD_LITTLE_ENDIAN BIT(4)
#define VD_SEPARATE_EN BIT(1)
#define VD_ENABLE BIT(0)
/* VD1_IF0_CANVAS0 */
#define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
#define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
#define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
/* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */
#define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
#define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
/* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */
#define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
#define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
/* VD1_IF0_GEN_REG2 */
#define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)
/* VIU_VD1_FMT_CTRL */
#define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)
#define VD_HORZ_FMT_EN BIT(20)
#define VD_VERT_RPT_LINE0 BIT(16)
#define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)
#define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
#define VD_VERT_FMT_EN BIT(0)
/* VPP_POSTBLEND_VD1_H_START_END */
#define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value)
#define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), value)
/* VPP_POSTBLEND_VD1_V_START_END */
#define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
#define VD_V_START(value) FIELD_PREP(GENMASK(27, 16), value)
/* VPP_BLEND_VD2_V_START_END */
#define VD2_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
#define VD2_V_START(value) FIELD_PREP(GENMASK(27, 16), value)
/* VIU_VD1_FMT_W */
#define VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)
#define VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)
/* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */
#define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value)
#define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value)
struct meson_overlay {
struct drm_plane base;
struct meson_drm *priv;
};
#define to_meson_overlay(x) container_of(x, struct meson_overlay, base)
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
static int meson_overlay_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct drm_crtc_state *crtc_state;
if (!state->crtc)
return 0;
crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
return drm_atomic_helper_check_plane_state(state, crtc_state,
FRAC_16_16(1, 5),
FRAC_16_16(5, 1),
true, true);
}
/* Takes a fixed 16.16 number and converts it to integer. */
static inline int64_t fixed16_to_int(int64_t value)
{
return value >> 16;
}
static const uint8_t skip_tab[6] = {
0x24, 0x04, 0x68, 0x48, 0x28, 0x08,
};
static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
int *repeat, bool interlace)
{
int offset_in = 0;
int offset_out = 0;
int repeat_skip = 0;
if (!interlace && ratio_y > (1 << 18))
offset_out = (1 * ratio_y) >> 10;
while ((offset_in + (4 << 8)) <= offset_out) {
repeat_skip++;
offset_in += 4 << 8;
}
*phase = (offset_out - offset_in) >> 2;
if (*phase > 0x100)
repeat_skip++;
*phase = *phase & 0xff;
if (repeat_skip > 5)
repeat_skip = 5;
*repeat = skip_tab[repeat_skip];
}
static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
struct drm_plane *plane,
bool interlace_mode)
{
struct drm_crtc_state *crtc_state = priv->crtc->state;
int video_top, video_left, video_width, video_height;
struct drm_plane_state *state = plane->state;
unsigned int vd_start_lines, vd_end_lines;
unsigned int hd_start_lines, hd_end_lines;
unsigned int crtc_height, crtc_width;
unsigned int vsc_startp, vsc_endp;
unsigned int hsc_startp, hsc_endp;
unsigned int crop_top, crop_left;
int vphase, vphase_repeat_skip;
unsigned int ratio_x, ratio_y;
int temp_height, temp_width;
unsigned int w_in, h_in;
int temp, start, end;
if (!crtc_state) {
DRM_ERROR("Invalid crtc_state\n");
return;
}
crtc_height = crtc_state->mode.vdisplay;
crtc_width = crtc_state->mode.hdisplay;
w_in = fixed16_to_int(state->src_w);
h_in = fixed16_to_int(state->src_h);
crop_top = fixed16_to_int(state->src_x);
crop_left = fixed16_to_int(state->src_x);
video_top = state->crtc_y;
video_left = state->crtc_x;
video_width = state->crtc_w;
video_height = state->crtc_h;
DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n",
crtc_width, crtc_height, interlace_mode);
DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n",
w_in, h_in, crop_top, crop_left);
DRM_DEBUG("video top %d left %d width %d height %d\n",
video_top, video_left, video_width, video_height);
ratio_x = (w_in << 18) / video_width;
ratio_y = (h_in << 18) / video_height;
if (ratio_x * video_width < (w_in << 18))
ratio_x++;
DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y);
meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip,
interlace_mode);
DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip);
/* Vertical */
start = video_top + video_height / 2 - ((h_in << 17) / ratio_y);
end = (h_in << 18) / ratio_y + start - 1;
if (video_top < 0 && start < 0)
vd_start_lines = (-(start) * ratio_y) >> 18;
else if (start < video_top)
vd_start_lines = ((video_top - start) * ratio_y) >> 18;
else
vd_start_lines = 0;
if (video_top < 0)
temp_height = min_t(unsigned int,
video_top + video_height - 1,
crtc_height - 1);
else
temp_height = min_t(unsigned int,
video_top + video_height - 1,
crtc_height - 1) - video_top + 1;
temp = vd_start_lines + (temp_height * ratio_y >> 18);
vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1);
vd_start_lines += crop_left;
vd_end_lines += crop_left;
/*
* TOFIX: Input frames are handled and scaled like progressive frames,
* proper handling of interlaced field input frames need to be figured
* out using the proper framebuffer flags set by userspace.
*/
if (interlace_mode) {
start >>= 1;
end >>= 1;
}
vsc_startp = max_t(int, start,
max_t(int, 0, video_top));
vsc_endp = min_t(int, end,
min_t(int, crtc_height - 1,
video_top + video_height - 1));
DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
/* Horizontal */
start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
end = (w_in << 18) / ratio_x + start - 1;
if (video_left < 0 && start < 0)
hd_start_lines = (-(start) * ratio_x) >> 18;
else if (start < video_left)
hd_start_lines = ((video_left - start) * ratio_x) >> 18;
else
hd_start_lines = 0;
if (video_left < 0)
temp_width = min_t(unsigned int,
video_left + video_width - 1,
crtc_width - 1);
else
temp_width = min_t(unsigned int,
video_left + video_width - 1,
crtc_width - 1) - video_left + 1;
temp = hd_start_lines + (temp_width * ratio_x >> 18);
hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1);
priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
hsc_startp = max_t(int, start, max_t(int, 0, video_left));
hsc_endp = min_t(int, end, min_t(int, crtc_width - 1,
video_left + video_width - 1));
hd_start_lines += crop_top;
hd_end_lines += crop_top;
DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
priv->viu.vpp_vsc_ini_phase = vphase << 8;
priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) |
vphase_repeat_skip;
priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) |
VD_X_END(hd_end_lines);
priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) |
VD_X_END(hd_end_lines >> 1);
priv->viu.viu_vd1_fmt_w =
VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
VD_Y_END(vd_end_lines);
priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) |
VD_Y_END(vd_end_lines >> 1);
priv->viu.vpp_pic_in_height = h_in;
priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) |
VD_H_END(hsc_endp);
priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) |
VD_H_END(hd_end_lines);
priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) |
VD_REGION24_START(hsc_startp);
priv->viu.vpp_hsc_region34_startp =
VD_REGION13_END(hsc_startp) |
VD_REGION24_START(hsc_endp - hsc_startp);
priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp;
priv->viu.vpp_hsc_start_phase_step = ratio_x << 6;
priv->viu.vpp_hsc_region1_phase_slope = 0;
priv->viu.vpp_hsc_region3_phase_slope = 0;
priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);
priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1;
priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) |
VD_V_END(vsc_endp);
priv->viu.vpp_blend_vd2_v_start_end =
VD2_V_START((vd_end_lines + 1) >> 1) |
VD2_V_END(vd_end_lines);
priv->viu.vpp_vsc_region12_startp = 0;
priv->viu.vpp_vsc_region34_startp =
VD_REGION13_END(vsc_endp - vsc_startp) |
VD_REGION24_START(vsc_endp - vsc_startp);
priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp;
priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
}
static void meson_overlay_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct meson_overlay *meson_overlay = to_meson_overlay(plane);
struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = state->fb;
struct meson_drm *priv = meson_overlay->priv;
struct drm_gem_cma_object *gem;
unsigned long flags;
bool interlace_mode;
DRM_DEBUG_DRIVER("\n");
/* Fallback is canvas provider is not available */
if (!priv->canvas) {
priv->canvas_id_vd1_0 = MESON_CANVAS_ID_VD1_0;
priv->canvas_id_vd1_1 = MESON_CANVAS_ID_VD1_1;
priv->canvas_id_vd1_2 = MESON_CANVAS_ID_VD1_2;
}
interlace_mode = state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
spin_lock_irqsave(&priv->drm->event_lock, flags);
priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
VD_URGENT_LUMA |
VD_HOLD_LINES(9) |
VD_CHRO_RPT_LASTL_CTRL |
VD_ENABLE;
/* Setup scaler params */
meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
priv->viu.vd1_if0_repeat_loop = 0;
priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0;
priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0;
priv->viu.vd1_range_map_y = 0;
priv->viu.vd1_range_map_cb = 0;
priv->viu.vd1_range_map_cr = 0;
/* Default values for RGB888/YUV444 */
priv->viu.vd1_if0_gen_reg2 = 0;
priv->viu.viu_vd1_fmt_ctrl = 0;
switch (fb->format->format) {
/* TOFIX DRM_FORMAT_RGB888 should be supported */
case DRM_FORMAT_YUYV:
priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1);
priv->viu.vd1_if0_canvas0 =
CANVAS_ADDR2(priv->canvas_id_vd1_0) |
CANVAS_ADDR1(priv->canvas_id_vd1_0) |
CANVAS_ADDR0(priv->canvas_id_vd1_0);
priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
VD_HORZ_FMT_EN |
VD_VERT_RPT_LINE0 |
VD_VERT_INITIAL_PHASE(12) |
VD_VERT_PHASE_STEP(16) | /* /2 */
VD_VERT_FMT_EN;
break;
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV21:
priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
priv->viu.vd1_if0_canvas0 =
CANVAS_ADDR2(priv->canvas_id_vd1_1) |
CANVAS_ADDR1(priv->canvas_id_vd1_1) |
CANVAS_ADDR0(priv->canvas_id_vd1_0);
if (fb->format->format == DRM_FORMAT_NV12)
priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1);
else
priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2);
priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
VD_HORZ_FMT_EN |
VD_VERT_RPT_LINE0 |
VD_VERT_INITIAL_PHASE(12) |
VD_VERT_PHASE_STEP(8) | /* /4 */
VD_VERT_FMT_EN;
break;
case DRM_FORMAT_YUV444:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YUV411:
case DRM_FORMAT_YUV410:
priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
priv->viu.vd1_if0_canvas0 =
CANVAS_ADDR2(priv->canvas_id_vd1_2) |
CANVAS_ADDR1(priv->canvas_id_vd1_1) |
CANVAS_ADDR0(priv->canvas_id_vd1_0);
switch (fb->format->format) {
case DRM_FORMAT_YUV422:
priv->viu.viu_vd1_fmt_ctrl =
VD_HORZ_Y_C_RATIO(1) | /* /2 */
VD_HORZ_FMT_EN |
VD_VERT_RPT_LINE0 |
VD_VERT_INITIAL_PHASE(12) |
VD_VERT_PHASE_STEP(16) | /* /2 */
VD_VERT_FMT_EN;
break;
case DRM_FORMAT_YUV420:
priv->viu.viu_vd1_fmt_ctrl =
VD_HORZ_Y_C_RATIO(1) | /* /2 */
VD_HORZ_FMT_EN |
VD_VERT_RPT_LINE0 |
VD_VERT_INITIAL_PHASE(12) |
VD_VERT_PHASE_STEP(8) | /* /4 */
VD_VERT_FMT_EN;
break;
case DRM_FORMAT_YUV411:
priv->viu.viu_vd1_fmt_ctrl =
VD_HORZ_Y_C_RATIO(2) | /* /4 */
VD_HORZ_FMT_EN |
VD_VERT_RPT_LINE0 |
VD_VERT_INITIAL_PHASE(12) |
VD_VERT_PHASE_STEP(16) | /* /2 */
VD_VERT_FMT_EN;
break;
case DRM_FORMAT_YUV410:
priv->viu.viu_vd1_fmt_ctrl =
VD_HORZ_Y_C_RATIO(2) | /* /4 */
VD_HORZ_FMT_EN |
VD_VERT_RPT_LINE0 |
VD_VERT_INITIAL_PHASE(12) |
VD_VERT_PHASE_STEP(8) | /* /4 */
VD_VERT_FMT_EN;
break;
}
break;
}
/* Update Canvas with buffer address */
priv->viu.vd1_planes = drm_format_num_planes(fb->format->format);
switch (priv->viu.vd1_planes) {
case 3:
gem = drm_fb_cma_get_gem_obj(fb, 2);
priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2];
priv->viu.vd1_stride2 = fb->pitches[2];
priv->viu.vd1_height2 =
drm_format_plane_height(fb->height,
fb->format->format, 2);
DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n",
priv->viu.vd1_addr2,
priv->viu.vd1_stride2,
priv->viu.vd1_height2);
/* fallthrough */
case 2:
gem = drm_fb_cma_get_gem_obj(fb, 1);
priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
priv->viu.vd1_stride1 = fb->pitches[1];
priv->viu.vd1_height1 =
drm_format_plane_height(fb->height,
fb->format->format, 1);
DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n",
priv->viu.vd1_addr1,
priv->viu.vd1_stride1,
priv->viu.vd1_height1);
/* fallthrough */
case 1:
gem = drm_fb_cma_get_gem_obj(fb, 0);
priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
priv->viu.vd1_stride0 = fb->pitches[0];
priv->viu.vd1_height0 =
drm_format_plane_height(fb->height,
fb->format->format, 0);
DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
priv->viu.vd1_addr0,
priv->viu.vd1_stride0,
priv->viu.vd1_height0);
}
priv->viu.vd1_enabled = true;
spin_unlock_irqrestore(&priv->drm->event_lock, flags);
DRM_DEBUG_DRIVER("\n");
}
static void meson_overlay_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct meson_overlay *meson_overlay = to_meson_overlay(plane);
struct meson_drm *priv = meson_overlay->priv;
DRM_DEBUG_DRIVER("\n");
priv->viu.vd1_enabled = false;
/* Disable VD1 */
writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
priv->io_base + _REG(VPP_MISC));
}
static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
.atomic_check = meson_overlay_atomic_check,
.atomic_disable = meson_overlay_atomic_disable,
.atomic_update = meson_overlay_atomic_update,
.prepare_fb = drm_gem_fb_prepare_fb,
};
static const struct drm_plane_funcs meson_overlay_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
.destroy = drm_plane_cleanup,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
};
static const uint32_t supported_drm_formats[] = {
DRM_FORMAT_YUYV,
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_YUV444,
DRM_FORMAT_YUV422,
DRM_FORMAT_YUV420,
DRM_FORMAT_YUV411,
DRM_FORMAT_YUV410,
};
int meson_overlay_create(struct meson_drm *priv)
{
struct meson_overlay *meson_overlay;
struct drm_plane *plane;
DRM_DEBUG_DRIVER("\n");
meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay),
GFP_KERNEL);
if (!meson_overlay)
return -ENOMEM;
meson_overlay->priv = priv;
plane = &meson_overlay->base;
drm_universal_plane_init(priv->drm, plane, 0xFF,
&meson_overlay_funcs,
supported_drm_formats,
ARRAY_SIZE(supported_drm_formats),
NULL,
DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
priv->overlay_plane = plane;
DRM_DEBUG_DRIVER("\n");
return 0;
}

14
drivers/gpu/drm/meson/meson_overlay.h Normal file
Visa fil

@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef __MESON_OVERLAY_H
#define __MESON_OVERLAY_H
#include "meson_drv.h"
int meson_overlay_create(struct meson_drm *priv);
#endif /* __MESON_OVERLAY_H */

201
drivers/gpu/drm/meson/meson_plane.c
Visa fil

@@ -24,6 +24,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/bitfield.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
@@ -31,6 +32,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_rect.h>
#include "meson_plane.h"
@@ -39,12 +41,51 @@
#include "meson_canvas.h"
#include "meson_registers.h"
/* OSD_SCI_WH_M1 */
#define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w)
#define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h)
/* OSD_SCO_H_START_END */
/* OSD_SCO_V_START_END */
#define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start)
#define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end)
/* OSD_SC_CTRL0 */
#define SC_CTRL0_PATH_EN BIT(3)
#define SC_CTRL0_SEL_OSD1 BIT(2)
/* OSD_VSC_CTRL0 */
#define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value)
#define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value)
#define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value)
#define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value)
#define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value)
#define VSC_PROG_INTERLACE BIT(23)
#define VSC_VERTICAL_SCALER_EN BIT(24)
/* OSD_VSC_INI_PHASE */
#define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom)
#define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top)
/* OSD_HSC_CTRL0 */
#define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value)
#define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value)
#define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value)
#define HSC_HORIZ_SCALER_EN BIT(22)
/* VPP_OSD_VSC_PHASE_STEP */
/* VPP_OSD_HSC_PHASE_STEP */
#define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value)
struct meson_plane {
struct drm_plane base;
struct meson_drm *priv;
bool enabled;
};
#define to_meson_plane(x) container_of(x, struct meson_plane, base)
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
static int meson_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -57,10 +98,15 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
/*
* Only allow :
* - Upscaling up to 5x, vertical and horizontal
* - Final coordinates must match crtc size
*/
return drm_atomic_helper_check_plane_state(state, crtc_state,
FRAC_16_16(1, 5),
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
true, true);
false, true);
}
/* Takes a fixed 16.16 number and converts it to integer. */
@@ -74,22 +120,20 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
{
struct meson_plane *meson_plane = to_meson_plane(plane);
struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = state->fb;
struct drm_rect dest = drm_plane_state_dest(state);
struct meson_drm *priv = meson_plane->priv;
struct drm_framebuffer *fb = state->fb;
struct drm_gem_cma_object *gem;
struct drm_rect src = {
.x1 = (state->src_x),
.y1 = (state->src_y),
.x2 = (state->src_x + state->src_w),
.y2 = (state->src_y + state->src_h),
};
struct drm_rect dest = {
.x1 = state->crtc_x,
.y1 = state->crtc_y,
.x2 = state->crtc_x + state->crtc_w,
.y2 = state->crtc_y + state->crtc_h,
};
unsigned long flags;
int vsc_ini_rcv_num, vsc_ini_rpt_p0_num;
int vsc_bot_rcv_num, vsc_bot_rpt_p0_num;
int hsc_ini_rcv_num, hsc_ini_rpt_p0_num;
int hf_phase_step, vf_phase_step;
int src_w, src_h, dst_w, dst_h;
int bot_ini_phase;
int hf_bank_len;
int vf_bank_len;
u8 canvas_id_osd1;
/*
* Update Coordinates
@@ -104,8 +148,13 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
(0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
OSD_BLK0_ENABLE;
if (priv->canvas)
canvas_id_osd1 = priv->canvas_id_osd1;
else
canvas_id_osd1 = MESON_CANVAS_ID_OSD1;
/* Set up BLK0 to point to the right canvas */
priv->viu.osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) |
OSD_ENDIANNESS_LE);
/* On GXBB, Use the old non-HDR RGB2YUV converter */
@@ -137,23 +186,115 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
break;
};
if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
priv->viu.osd1_interlace = true;
/* Default scaler parameters */
vsc_bot_rcv_num = 0;
vsc_bot_rpt_p0_num = 0;
hf_bank_len = 4;
vf_bank_len = 4;
if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
vsc_bot_rcv_num = 6;
vsc_bot_rpt_p0_num = 2;
}
hsc_ini_rcv_num = hf_bank_len;
vsc_ini_rcv_num = vf_bank_len;
hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1;
vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1;
src_w = fixed16_to_int(state->src_w);
src_h = fixed16_to_int(state->src_h);
dst_w = state->crtc_w;
dst_h = state->crtc_h;
/*
* When the output is interlaced, the OSD must switch between
* each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
* at each vsync.
* But the vertical scaler can provide such funtionnality if
* is configured for 2:1 scaling with interlace options enabled.
*/
if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
dest.y1 /= 2;
dest.y2 /= 2;
} else
priv->viu.osd1_interlace = false;
dst_h /= 2;
}
hf_phase_step = ((src_w << 18) / dst_w) << 6;
vf_phase_step = (src_h << 20) / dst_h;
if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
bot_ini_phase = ((vf_phase_step / 2) >> 4);
else
bot_ini_phase = 0;
vf_phase_step = (vf_phase_step << 4);
/* In interlaced mode, scaler is always active */
if (src_h != dst_h || src_w != dst_w) {
priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
SCI_WH_M1_H(src_h - 1);
priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
SCO_HV_END(dest.x2 - 1);
priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
SCO_HV_END(dest.y2 - 1);
/* Enable OSD Scaler */
priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
} else {
priv->viu.osd_sc_i_wh_m1 = 0;
priv->viu.osd_sc_o_h_start_end = 0;
priv->viu.osd_sc_o_v_start_end = 0;
priv->viu.osd_sc_ctrl0 = 0;
}
/* In interlaced mode, vertical scaler is always active */
if (src_h != dst_h) {
priv->viu.osd_sc_v_ctrl0 =
VSC_BANK_LEN(vf_bank_len) |
VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) |
VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) |
VSC_VERTICAL_SCALER_EN;
if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
priv->viu.osd_sc_v_ctrl0 |=
VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) |
VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) |
VSC_PROG_INTERLACE;
priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
} else {
priv->viu.osd_sc_v_ctrl0 = 0;
priv->viu.osd_sc_v_phase_step = 0;
priv->viu.osd_sc_v_ini_phase = 0;
}
/* Horizontal scaler is only used if width does not match */
if (src_w != dst_w) {
priv->viu.osd_sc_h_ctrl0 =
HSC_BANK_LENGTH(hf_bank_len) |
HSC_INI_RCV_NUM0(hsc_ini_rcv_num) |
HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) |
HSC_HORIZ_SCALER_EN;
priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
priv->viu.osd_sc_h_ini_phase = 0;
} else {
priv->viu.osd_sc_h_ctrl0 = 0;
priv->viu.osd_sc_h_phase_step = 0;
priv->viu.osd_sc_h_ini_phase = 0;
}
/*
* The format of these registers is (x2 << 16 | x1),
* where x2 is exclusive.
* e.g. +30x1920 would be (1919 << 16) | 30
*/
priv->viu.osd1_blk0_cfg[1] = ((fixed16_to_int(src.x2) - 1) << 16) |
fixed16_to_int(src.x1);
priv->viu.osd1_blk0_cfg[2] = ((fixed16_to_int(src.y2) - 1) << 16) |
fixed16_to_int(src.y1);
priv->viu.osd1_blk0_cfg[1] =
((fixed16_to_int(state->src.x2) - 1) << 16) |
fixed16_to_int(state->src.x1);
priv->viu.osd1_blk0_cfg[2] =
((fixed16_to_int(state->src.y2) - 1) << 16) |
fixed16_to_int(state->src.y1);
priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
@@ -164,6 +305,15 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
priv->viu.osd1_stride = fb->pitches[0];
priv->viu.osd1_height = fb->height;
if (!meson_plane->enabled) {
/* Reset OSD1 before enabling it on GXL+ SoCs */
if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
meson_viu_osd1_reset(priv);
meson_plane->enabled = true;
}
spin_unlock_irqrestore(&priv->drm->event_lock, flags);
}
@@ -177,12 +327,15 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
priv->io_base + _REG(VPP_MISC));
meson_plane->enabled = false;
}
static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
.atomic_check = meson_plane_atomic_check,
.atomic_disable = meson_plane_atomic_disable,
.atomic_update = meson_plane_atomic_update,
.prepare_fb = drm_gem_fb_prepare_fb,
};
static const struct drm_plane_funcs meson_plane_funcs = {

3
drivers/gpu/drm/meson/meson_registers.h
Visa fil

@@ -286,6 +286,7 @@
#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d
#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e
#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f
#define VD1_IF0_GEN_REG3 0x1aa7
#define VIU_OSD1_EOTF_CTL 0x1ad4
#define VIU_OSD1_EOTF_COEF00_01 0x1ad5
#define VIU_OSD1_EOTF_COEF02_10 0x1ad6
@@ -297,6 +298,7 @@
#define VIU_OSD1_OETF_CTL 0x1adc
#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
#define AFBC_ENABLE 0x1ae0
/* vpp */
#define VPP_DUMMY_DATA 0x1d00
@@ -349,6 +351,7 @@
#define VPP_VD2_PREBLEND BIT(15)
#define VPP_OSD1_PREBLEND BIT(16)
#define VPP_OSD2_PREBLEND BIT(17)
#define VPP_COLOR_MNG_ENABLE BIT(28)
#define VPP_OFIFO_SIZE 0x1d27
#define VPP_FIFO_STATUS 0x1d28
#define VPP_SMOKE_CTRL 0x1d29

127
drivers/gpu/drm/meson/meson_vclk.c
Visa fil

@@ -117,6 +117,8 @@
#define HDMI_PLL_RESET BIT(28)
#define HDMI_PLL_LOCK BIT(31)
#define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001)
/* VID PLL Dividers */
enum {
VID_PLL_DIV_1 = 0,
@@ -323,7 +325,7 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
enum {
/* PLL O1 O2 O3 VP DV EN TX */
/* 4320 /4 /4 /1 /5 /1 => /2 /2 */
MESON_VCLK_HDMI_ENCI_54000 = 1,
MESON_VCLK_HDMI_ENCI_54000 = 0,
/* 4320 /4 /4 /1 /5 /1 => /1 /2 */
MESON_VCLK_HDMI_DDR_54000,
/* 2970 /4 /1 /1 /5 /1 => /1 /2 */
@@ -339,6 +341,7 @@ enum {
};
struct meson_vclk_params {
unsigned int pixel_freq;
unsigned int pll_base_freq;
unsigned int pll_od1;
unsigned int pll_od2;
@@ -347,6 +350,7 @@ struct meson_vclk_params {
unsigned int vclk_div;
} params[] = {
[MESON_VCLK_HDMI_ENCI_54000] = {
.pixel_freq = 54000,
.pll_base_freq = 4320000,
.pll_od1 = 4,
.pll_od2 = 4,
@@ -355,6 +359,7 @@ struct meson_vclk_params {
.vclk_div = 1,
},
[MESON_VCLK_HDMI_DDR_54000] = {
.pixel_freq = 54000,
.pll_base_freq = 4320000,
.pll_od1 = 4,
.pll_od2 = 4,
@@ -363,6 +368,7 @@ struct meson_vclk_params {
.vclk_div = 1,
},
[MESON_VCLK_HDMI_DDR_148500] = {
.pixel_freq = 148500,
.pll_base_freq = 2970000,
.pll_od1 = 4,
.pll_od2 = 1,
@@ -371,6 +377,7 @@ struct meson_vclk_params {
.vclk_div = 1,
},
[MESON_VCLK_HDMI_74250] = {
.pixel_freq = 74250,
.pll_base_freq = 2970000,
.pll_od1 = 2,
.pll_od2 = 2,
@@ -379,6 +386,7 @@ struct meson_vclk_params {
.vclk_div = 1,
},
[MESON_VCLK_HDMI_148500] = {
.pixel_freq = 148500,
.pll_base_freq = 2970000,
.pll_od1 = 1,
.pll_od2 = 2,
@@ -387,6 +395,7 @@ struct meson_vclk_params {
.vclk_div = 1,
},
[MESON_VCLK_HDMI_297000] = {
.pixel_freq = 297000,
.pll_base_freq = 2970000,
.pll_od1 = 1,
.pll_od2 = 1,
@@ -395,6 +404,7 @@ struct meson_vclk_params {
.vclk_div = 2,
},
[MESON_VCLK_HDMI_594000] = {
.pixel_freq = 594000,
.pll_base_freq = 5940000,
.pll_od1 = 1,
.pll_od2 = 1,
@@ -402,6 +412,7 @@ struct meson_vclk_params {
.vid_pll_div = VID_PLL_DIV_5,
.vclk_div = 1,
},
{ /* sentinel */ },
};
static inline unsigned int pll_od_to_reg(unsigned int od)
@@ -626,12 +637,37 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
pll_freq);
}
enum drm_mode_status
meson_vclk_vic_supported_freq(unsigned int freq)
{
int i;
DRM_DEBUG_DRIVER("freq = %d\n", freq);
for (i = 0 ; params[i].pixel_freq ; ++i) {
DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
i, params[i].pixel_freq,
FREQ_1000_1001(params[i].pixel_freq));
/* Match strict frequency */
if (freq == params[i].pixel_freq)
return MODE_OK;
/* Match 1000/1001 variant */
if (freq == FREQ_1000_1001(params[i].pixel_freq))
return MODE_OK;
}
return MODE_CLOCK_RANGE;
}
EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq);
static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
unsigned int od1, unsigned int od2, unsigned int od3,
unsigned int vid_pll_div, unsigned int vclk_div,
unsigned int hdmi_tx_div, unsigned int venc_div,
bool hdmi_use_enci)
bool hdmi_use_enci, bool vic_alternate_clock)
{
unsigned int m = 0, frac = 0;
/* Set HDMI-TX sys clock */
regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
CTS_HDMI_SYS_SEL_MASK, 0);
@@ -646,34 +682,38 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
switch (pll_base_freq) {
case 2970000:
meson_hdmi_pll_set_params(priv, 0x3d, 0xe00,
od1, od2, od3);
m = 0x3d;
frac = vic_alternate_clock ? 0xd02 : 0xe00;
break;
case 4320000:
meson_hdmi_pll_set_params(priv, 0x5a, 0,
od1, od2, od3);
m = vic_alternate_clock ? 0x59 : 0x5a;
frac = vic_alternate_clock ? 0xe8f : 0;
break;
case 5940000:
meson_hdmi_pll_set_params(priv, 0x7b, 0xc00,
od1, od2, od3);
m = 0x7b;
frac = vic_alternate_clock ? 0xa05 : 0xc00;
break;
}
meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
switch (pll_base_freq) {
case 2970000:
meson_hdmi_pll_set_params(priv, 0x7b, 0x300,
od1, od2, od3);
m = 0x7b;
frac = vic_alternate_clock ? 0x281 : 0x300;
break;
case 4320000:
meson_hdmi_pll_set_params(priv, 0xb4, 0,
od1, od2, od3);
m = vic_alternate_clock ? 0xb3 : 0xb4;
frac = vic_alternate_clock ? 0x347 : 0;
break;
case 5940000:
meson_hdmi_pll_set_params(priv, 0xf7, 0x200,
od1, od2, od3);
m = 0xf7;
frac = vic_alternate_clock ? 0x102 : 0x200;
break;
}
meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
}
/* Setup vid_pll divider */
@@ -826,6 +866,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int vclk_freq, unsigned int venc_freq,
unsigned int dac_freq, bool hdmi_use_enci)
{
bool vic_alternate_clock = false;
unsigned int freq;
unsigned int hdmi_tx_div;
unsigned int venc_div;
@@ -843,7 +884,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
* - encp encoder
*/
meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
VID_PLL_DIV_5, 2, 1, 1, false);
VID_PLL_DIV_5, 2, 1, 1, false, false);
return;
}
@@ -863,31 +904,35 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
return;
}
switch (vclk_freq) {
case 54000:
if (hdmi_use_enci)
freq = MESON_VCLK_HDMI_ENCI_54000;
else
freq = MESON_VCLK_HDMI_DDR_54000;
break;
case 74250:
freq = MESON_VCLK_HDMI_74250;
break;
case 148500:
if (dac_freq != 148500)
freq = MESON_VCLK_HDMI_DDR_148500;
else
freq = MESON_VCLK_HDMI_148500;
break;
case 297000:
freq = MESON_VCLK_HDMI_297000;
break;
case 594000:
freq = MESON_VCLK_HDMI_594000;
break;
default:
pr_err("Fatal Error, invalid HDMI vclk freq %d\n",
vclk_freq);
for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
if (vclk_freq == params[freq].pixel_freq ||
vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
if (vclk_freq != params[freq].pixel_freq)
vic_alternate_clock = true;
else
vic_alternate_clock = false;
if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
!hdmi_use_enci)
continue;
if (freq == MESON_VCLK_HDMI_DDR_54000 &&
hdmi_use_enci)
continue;
if (freq == MESON_VCLK_HDMI_DDR_148500 &&
dac_freq == vclk_freq)
continue;
if (freq == MESON_VCLK_HDMI_148500 &&
dac_freq != vclk_freq)
continue;
break;
}
}
if (!params[freq].pixel_freq) {
pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
return;
}
@@ -895,6 +940,6 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
params[freq].pll_od1, params[freq].pll_od2,
params[freq].pll_od3, params[freq].vid_pll_div,
params[freq].vclk_div, hdmi_tx_div, venc_div,
hdmi_use_enci);
hdmi_use_enci, vic_alternate_clock);
}
EXPORT_SYMBOL_GPL(meson_vclk_setup);

2
drivers/gpu/drm/meson/meson_vclk.h
Visa fil

@@ -32,6 +32,8 @@ enum {
enum drm_mode_status
meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
enum drm_mode_status
meson_vclk_vic_supported_freq(unsigned int freq);
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int vclk_freq, unsigned int venc_freq,

129
drivers/gpu/drm/meson/meson_venc.c
Visa fil

@@ -698,6 +698,132 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
},
};
union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p24 = {
.encp = {
.dvi_settings = 0x1,
.video_mode = 0x4040,
.video_mode_adv = 0x8,
/* video_sync_mode */
/* video_yc_dly */
/* video_rgb_ctrl */
.video_filt_ctrl = 0x1000,
.video_filt_ctrl_present = true,
/* video_ofld_voav_ofst */
.yfp1_htime = 140,
.yfp2_htime = 140+3840,
.max_pxcnt = 3840+1660-1,
.hspuls_begin = 2156+1920,
.hspuls_end = 44,
.hspuls_switch = 44,
.vspuls_begin = 140,
.vspuls_end = 2059+1920,
.vspuls_bline = 0,
.vspuls_eline = 4,
.havon_begin = 148,
.havon_end = 3987,
.vavon_bline = 89,
.vavon_eline = 2248,
/* eqpuls_begin */
/* eqpuls_end */
/* eqpuls_bline */
/* eqpuls_eline */
.hso_begin = 44,
.hso_end = 2156+1920,
.vso_begin = 2100+1920,
.vso_end = 2164+1920,
.vso_bline = 51,
.vso_eline = 53,
.vso_eline_present = true,
/* sy_val */
/* sy2_val */
.max_lncnt = 2249,
},
};
union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p25 = {
.encp = {
.dvi_settings = 0x1,
.video_mode = 0x4040,
.video_mode_adv = 0x8,
/* video_sync_mode */
/* video_yc_dly */
/* video_rgb_ctrl */
.video_filt_ctrl = 0x1000,
.video_filt_ctrl_present = true,
/* video_ofld_voav_ofst */
.yfp1_htime = 140,
.yfp2_htime = 140+3840,
.max_pxcnt = 3840+1440-1,
.hspuls_begin = 2156+1920,
.hspuls_end = 44,
.hspuls_switch = 44,
.vspuls_begin = 140,
.vspuls_end = 2059+1920,
.vspuls_bline = 0,
.vspuls_eline = 4,
.havon_begin = 148,
.havon_end = 3987,
.vavon_bline = 89,
.vavon_eline = 2248,
/* eqpuls_begin */
/* eqpuls_end */
/* eqpuls_bline */
/* eqpuls_eline */
.hso_begin = 44,
.hso_end = 2156+1920,
.vso_begin = 2100+1920,
.vso_end = 2164+1920,
.vso_bline = 51,
.vso_eline = 53,
.vso_eline_present = true,
/* sy_val */
/* sy2_val */
.max_lncnt = 2249,
},
};
union meson_hdmi_venc_mode meson_hdmi_encp_mode_2160p30 = {
.encp = {
.dvi_settings = 0x1,
.video_mode = 0x4040,
.video_mode_adv = 0x8,
/* video_sync_mode */
/* video_yc_dly */
/* video_rgb_ctrl */
.video_filt_ctrl = 0x1000,
.video_filt_ctrl_present = true,
/* video_ofld_voav_ofst */
.yfp1_htime = 140,
.yfp2_htime = 140+3840,
.max_pxcnt = 3840+560-1,
.hspuls_begin = 2156+1920,
.hspuls_end = 44,
.hspuls_switch = 44,
.vspuls_begin = 140,
.vspuls_end = 2059+1920,
.vspuls_bline = 0,
.vspuls_eline = 4,
.havon_begin = 148,
.havon_end = 3987,
.vavon_bline = 89,
.vavon_eline = 2248,
/* eqpuls_begin */
/* eqpuls_end */
/* eqpuls_bline */
/* eqpuls_eline */
.hso_begin = 44,
.hso_end = 2156+1920,
.vso_begin = 2100+1920,
.vso_end = 2164+1920,
.vso_bline = 51,
.vso_eline = 53,
.vso_eline_present = true,
/* sy_val */
/* sy2_val */
.max_lncnt = 2249,
},
};
struct meson_hdmi_venc_vic_mode {
unsigned int vic;
union meson_hdmi_venc_mode *mode;
@@ -719,6 +845,9 @@ struct meson_hdmi_venc_vic_mode {
{ 34, &meson_hdmi_encp_mode_1080p30 },
{ 31, &meson_hdmi_encp_mode_1080p50 },
{ 16, &meson_hdmi_encp_mode_1080p60 },
{ 93, &meson_hdmi_encp_mode_2160p24 },
{ 94, &meson_hdmi_encp_mode_2160p25 },
{ 95, &meson_hdmi_encp_mode_2160p30 },
{ 0, NULL}, /* sentinel */
};

42
drivers/gpu/drm/meson/meson_viu.c
Visa fil

@@ -296,6 +296,33 @@ static void meson_viu_load_matrix(struct meson_drm *priv)
true);
}
/* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */
void meson_viu_osd1_reset(struct meson_drm *priv)
{
uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2;
/* Save these 2 registers state */
osd1_fifo_ctrl_stat = readl_relaxed(
priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
osd1_ctrl_stat2 = readl_relaxed(
priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
/* Reset OSD1 */
writel_bits_relaxed(BIT(0), BIT(0),
priv->io_base + _REG(VIU_SW_RESET));
writel_bits_relaxed(BIT(0), 0,
priv->io_base + _REG(VIU_SW_RESET));
/* Rewrite these registers state lost in the reset */
writel_relaxed(osd1_fifo_ctrl_stat,
priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(osd1_ctrl_stat2,
priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
/* Reload the conversion matrix */
meson_viu_load_matrix(priv);
}
void meson_viu_init(struct meson_drm *priv)
{
uint32_t reg;
@@ -329,6 +356,21 @@ void meson_viu_init(struct meson_drm *priv)
0xff << OSD_REPLACE_SHIFT,
priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
/* Disable VD1 AFBC */
/* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 */
writel_bits_relaxed(0x7 << 16, 0,
priv->io_base + _REG(VIU_MISC_CTRL0));
/* afbc vd1 set=0 */
writel_bits_relaxed(BIT(20), 0,
priv->io_base + _REG(VIU_MISC_CTRL0));
writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
writel_relaxed(0x00FF00C0,
priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE));
writel_relaxed(0x00FF00C0,
priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
priv->viu.osd1_enabled = false;
priv->viu.osd1_commit = false;
priv->viu.osd1_interlace = false;

1
drivers/gpu/drm/meson/meson_viu.h
Visa fil

@@ -59,6 +59,7 @@
#define OSD_REPLACE_EN BIT(14)
#define OSD_REPLACE_SHIFT 6
void meson_viu_osd1_reset(struct meson_drm *priv);
void meson_viu_init(struct meson_drm *priv);
#endif /* __MESON_VIU_H */

90
drivers/gpu/drm/meson/meson_vpp.c
Visa fil

@@ -51,52 +51,6 @@ void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
}
/*
* When the output is interlaced, the OSD must switch between
* each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
* at each vsync.
* But the vertical scaler can provide such funtionnality if
* is configured for 2:1 scaling with interlace options enabled.
*/
void meson_vpp_setup_interlace_vscaler_osd1(struct meson_drm *priv,
struct drm_rect *input)
{
writel_relaxed(BIT(3) /* Enable scaler */ |
BIT(2), /* Select OSD1 */
priv->io_base + _REG(VPP_OSD_SC_CTRL0));
writel_relaxed(((drm_rect_width(input) - 1) << 16) |
(drm_rect_height(input) - 1),
priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
/* 2:1 scaling */
writel_relaxed(((input->x1) << 16) | (input->x2),
priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
writel_relaxed(((input->y1 >> 1) << 16) | (input->y2 >> 1),
priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
/* 2:1 scaling values */
writel_relaxed(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
writel_relaxed(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
writel_relaxed((4 << 0) /* osd_vsc_bank_length */ |
(4 << 3) /* osd_vsc_top_ini_rcv_num0 */ |
(1 << 8) /* osd_vsc_top_rpt_p0_num0 */ |
(6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
(2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
BIT(23) /* osd_prog_interlace */ |
BIT(24), /* Enable vertical scaler */
priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
}
void meson_vpp_disable_interlace_vscaler_osd1(struct meson_drm *priv)
{
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
}
static unsigned int vpp_filter_coefs_4point_bspline[] = {
0x15561500, 0x14561600, 0x13561700, 0x12561800,
0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
@@ -122,6 +76,31 @@ static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
priv->io_base + _REG(VPP_OSD_SCALE_COEF));
}
static const uint32_t vpp_filter_coefs_bicubic[] = {
0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
0xf84848f8
};
static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
const unsigned int *coefs,
bool is_horizontal)
{
int i;
writel_relaxed(is_horizontal ? BIT(8) : 0,
priv->io_base + _REG(VPP_SCALE_COEF_IDX));
for (i = 0; i < 33; i++)
writel_relaxed(coefs[i],
priv->io_base + _REG(VPP_SCALE_COEF));
}
void meson_vpp_init(struct meson_drm *priv)
{
/* set dummy data default YUV black */
@@ -150,17 +129,34 @@ void meson_vpp_init(struct meson_drm *priv)
/* Force all planes off */
writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND, 0,
VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
priv->io_base + _REG(VPP_MISC));
/* Setup default VD settings */
writel_relaxed(4096,
priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
writel_relaxed(4096,
priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
/* Disable Scalers */
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
writel_relaxed(4 | (4 << 8) | BIT(15),
priv->io_base + _REG(VPP_SC_MISC));
writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL));
/* Write in the proper filter coefficients. */
meson_vpp_write_scaling_filter_coefs(priv,
vpp_filter_coefs_4point_bspline, false);
meson_vpp_write_scaling_filter_coefs(priv,
vpp_filter_coefs_4point_bspline, true);
/* Write the VD proper filter coefficients. */
meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
false);
meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
true);
}