Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "Core: - shared fencing staging removal - drop transactional atomic helpers and move helpers to new location - DP/MST atomic cleanup - Leasing cleanups and drop EXPORT_SYMBOL - Convert drivers to atomic helpers and generic fbdev. - removed deprecated obj_ref/unref in favour of get/put - Improve dumb callback documentation - MODESET_LOCK_BEGIN/END helpers panels: - CDTech panels, Banana Pi Panel, DLC1010GIG, - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA, - Himax HX8357D, simulated RTSM AEMv8. - GPD Win2 panel - AUO G101EVN010 vgem: - render node support ttm: - move global init out of drivers - fix LRU handling for ghost objects - Support for simultaneous submissions to multiple engines scheduler: - timeout/fault handling changes to help GPU recovery - helpers for hw with preemption support i915: - Scaler/Watermark fixes - DP MST + powerwell fixes - PSR fixes - Break long get/put shmemfs pages - Icelake fixes - Icelake DSI video mode enablement - Engine workaround improvements amdgpu: - freesync support - GPU reset enabled on CI, VI, SOC15 dGPUs - ABM support in DC - KFD support for vega12/polaris12 - SDMA paging queue on vega - More amdkfd code sharing - DCC scanout on GFX9 - DC kerneldoc - Updated SMU firmware for GFX8 chips - XGMI PSP + hive reset support - GPU reset - DC trace support - Powerplay updates for newer Polaris - Cursor plane update fast path - kfd dma-buf support virtio-gpu: - add EDID support vmwgfx: - pageflip with damage support nouveau: - Initial Turing TU104/TU106 modesetting support msm: - a2xx gpu support for apq8060 and imx5 - a2xx gpummu support - mdp4 display support for apq8060 - DPU fixes and cleanups - enhanced profiling support - debug object naming interface - get_iova/page pinning decoupling tegra: - Tegra194 host1x, VIC and display support enabled - Audio over HDMI for Tegra186 and Tegra194 exynos: - DMA/IOMMU refactoring - plane alpha + blend mode support - Color format fixes for mixer driver rcar-du: - R8A7744 and R8A77470 support - R8A77965 LVDS support imx: - fbdev emulation fix - multi-tiled scalling fixes - SPDX identifiers rockchip - dw_hdmi support - dw-mipi-dsi + dual dsi support - mailbox read size fix qxl: - fix cursor pinning vc4: - YUV support (scaling + cursor) v3d: - enable TFU (Texture Formatting Unit) mali-dp: - add support for linear tiled formats sun4i: - Display Engine 3 support - H6 DE3 mixer 0 support - H6 display engine support - dw-hdmi support - H6 HDMI phy support - implicit fence waiting - BGRX8888 support meson: - Overlay plane support - implicit fence waiting - HDMI 1.4 4k modes bridge: - i2c fixes for sii902x" * tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits) drm/amd/display: Add fast path for cursor plane updates drm/amdgpu: Enable GPU recovery by default for CI drm/amd/display: Fix duplicating scaling/underscan connector state drm/amd/display: Fix unintialized max_bpc state values Revert "drm/amd/display: Set RMX_ASPECT as default" drm/amdgpu: Fix stub function name drm/msm/dpu: Fix clock issue after bind failure drm/msm/dpu: Clean up dpu_media_info.h static inline functions drm/msm/dpu: Further cleanups for static inline functions drm/msm/dpu: Cleanup the debugfs functions drm/msm/dpu: Remove dpu_irq and unused functions drm/msm: Make irq_postinstall optional drm/msm/dpu: Cleanup callers of dpu_hw_blk_init drm/msm/dpu: Remove unused functions drm/msm/dpu: Remove dpu_crtc_is_enabled() drm/msm/dpu: Remove dpu_crtc_get_mixer_height drm/msm/dpu: Remove dpu_dbg drm/msm: dpu: Remove crtc_lock drm/msm: dpu: Remove vblank_requested flag from dpu_crtc drm/msm: dpu: Separate crtc assignment from vblank enable ...
This commit is contained in:
Linus Torvalds
@@ -75,11 +75,14 @@
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#include "amdgpu_sdma.h"
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#include "amdgpu_dm.h"
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#include "amdgpu_virt.h"
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#include "amdgpu_csa.h"
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#include "amdgpu_gart.h"
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#include "amdgpu_debugfs.h"
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#include "amdgpu_job.h"
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#include "amdgpu_bo_list.h"
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#include "amdgpu_gem.h"
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#include "amdgpu_doorbell.h"
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#include "amdgpu_amdkfd.h"
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#define MAX_GPU_INSTANCE 16
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@@ -161,6 +164,7 @@ extern int amdgpu_si_support;
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extern int amdgpu_cik_support;
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#endif
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#define AMDGPU_VM_MAX_NUM_CTX 4096
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#define AMDGPU_SG_THRESHOLD (256*1024*1024)
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#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
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#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
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@@ -359,123 +363,6 @@ struct amdgpu_sa_bo {
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int amdgpu_fence_slab_init(void);
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void amdgpu_fence_slab_fini(void);
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/*
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* GPU doorbell structures, functions & helpers
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*/
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typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
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{
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AMDGPU_DOORBELL_KIQ = 0x000,
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AMDGPU_DOORBELL_HIQ = 0x001,
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AMDGPU_DOORBELL_DIQ = 0x002,
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AMDGPU_DOORBELL_MEC_RING0 = 0x010,
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AMDGPU_DOORBELL_MEC_RING1 = 0x011,
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AMDGPU_DOORBELL_MEC_RING2 = 0x012,
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AMDGPU_DOORBELL_MEC_RING3 = 0x013,
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AMDGPU_DOORBELL_MEC_RING4 = 0x014,
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AMDGPU_DOORBELL_MEC_RING5 = 0x015,
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AMDGPU_DOORBELL_MEC_RING6 = 0x016,
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AMDGPU_DOORBELL_MEC_RING7 = 0x017,
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AMDGPU_DOORBELL_GFX_RING0 = 0x020,
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AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
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AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
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AMDGPU_DOORBELL_IH = 0x1E8,
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AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
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AMDGPU_DOORBELL_INVALID = 0xFFFF
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} AMDGPU_DOORBELL_ASSIGNMENT;
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struct amdgpu_doorbell {
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/* doorbell mmio */
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resource_size_t base;
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resource_size_t size;
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u32 __iomem *ptr;
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u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
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};
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/*
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* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
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*/
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typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
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{
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/*
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* All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
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* a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
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* Compute related doorbells are allocated from 0x00 to 0x8a
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*/
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/* kernel scheduling */
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AMDGPU_DOORBELL64_KIQ = 0x00,
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/* HSA interface queue and debug queue */
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AMDGPU_DOORBELL64_HIQ = 0x01,
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AMDGPU_DOORBELL64_DIQ = 0x02,
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/* Compute engines */
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AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
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AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
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AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
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AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
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AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
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AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
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AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
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AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
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/* User queue doorbell range (128 doorbells) */
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AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
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AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
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/* Graphics engine */
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AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
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/*
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* Other graphics doorbells can be allocated here: from 0x8c to 0xdf
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* Graphics voltage island aperture 1
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* default non-graphics QWORD index is 0xe0 - 0xFF inclusive
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*/
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/* sDMA engines reserved from 0xe0 -oxef */
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AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xE0,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1,
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AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xE8,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9,
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/* For vega10 sriov, the sdma doorbell must be fixed as follow
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* to keep the same setting with host driver, or it will
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* happen conflicts
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*/
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AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 = 0xF0,
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AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
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AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 = 0xF2,
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AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
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/* Interrupt handler */
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AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
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AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
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AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
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/* VCN engine use 32 bits doorbell */
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AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
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AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
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AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
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AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
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/* overlap the doorbell assignment with VCN as they are mutually exclusive
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* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
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*/
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AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
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AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
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AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
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AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
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AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
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AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
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AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
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AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
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AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
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AMDGPU_DOORBELL64_INVALID = 0xFFFF
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} AMDGPU_DOORBELL64_ASSIGNMENT;
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/*
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* IRQS.
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*/
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@@ -653,6 +540,8 @@ struct amdgpu_asic_funcs {
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struct amdgpu_ring *ring);
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/* check if the asic needs a full reset of if soft reset will work */
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bool (*need_full_reset)(struct amdgpu_device *adev);
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/* initialize doorbell layout for specific asic*/
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void (*init_doorbell_index)(struct amdgpu_device *adev);
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};
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/*
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@@ -831,7 +720,6 @@ struct amdgpu_device {
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bool need_dma32;
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bool need_swiotlb;
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bool accel_working;
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struct work_struct reset_work;
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struct notifier_block acpi_nb;
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struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
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struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
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@@ -976,6 +864,9 @@ struct amdgpu_device {
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/* GDS */
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struct amdgpu_gds gds;
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/* KFD */
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struct amdgpu_kfd_dev kfd;
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/* display related functionality */
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struct amdgpu_display_manager dm;
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@@ -989,9 +880,6 @@ struct amdgpu_device {
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atomic64_t visible_pin_size;
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atomic64_t gart_pin_size;
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/* amdkfd interface */
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struct kfd_dev *kfd;
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/* soc15 register offset based on ip, instance and segment */
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uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
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@@ -1023,6 +911,10 @@ struct amdgpu_device {
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unsigned long last_mm_index;
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bool in_gpu_reset;
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struct mutex lock_reset;
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struct amdgpu_doorbell_index doorbell_index;
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int asic_reset_res;
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struct work_struct xgmi_reset_work;
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};
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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@@ -1047,11 +939,6 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
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u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
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void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
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u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
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void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
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u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
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void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
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bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
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bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
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@@ -1113,11 +1000,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
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#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
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#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
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#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
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#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
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#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
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#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
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#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
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#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
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@@ -1159,6 +1041,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
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#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
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#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
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#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
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#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
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/* Common functions */
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bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
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@@ -1219,12 +1102,6 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
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long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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/*
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* functions used by amdgpu_xgmi.c
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*/
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int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
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/*
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* functions used by amdgpu_encoder.c
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*/
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@@ -1252,6 +1129,9 @@ bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *ade
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int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
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struct amdgpu_dm_backlight_caps *caps);
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#else
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static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
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static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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