regulator/mfd: Support ROHM BD71847 power management IC
BD71847 is reduced version of BD71837. DVS bucks 3 and 4 are removed as is LDO7. Voltage ranges of some regulators are expanded. Add initial support for BD71847 with BD71837 driver. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Matti Vaittinen
committed by
Mark Brown
Mark Brown
parent
2e0fe4d0c6
commit
494edd266b
@@ -7,106 +7,125 @@
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#include <linux/regmap.h>
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enum {
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BD71837_BUCK1 = 0,
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BD71837_BUCK2,
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BD71837_BUCK3,
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BD71837_BUCK4,
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BD71837_BUCK5,
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BD71837_BUCK6,
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BD71837_BUCK7,
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BD71837_BUCK8,
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BD71837_LDO1,
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BD71837_LDO2,
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BD71837_LDO3,
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BD71837_LDO4,
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BD71837_LDO5,
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BD71837_LDO6,
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BD71837_LDO7,
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BD71837_REGULATOR_CNT,
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BD718XX_TYPE_BD71837 = 0,
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BD718XX_TYPE_BD71847,
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BD718XX_TYPE_AMOUNT
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};
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#define BD71837_BUCK1_VOLTAGE_NUM 0x40
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#define BD71837_BUCK2_VOLTAGE_NUM 0x40
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#define BD71837_BUCK3_VOLTAGE_NUM 0x40
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#define BD71837_BUCK4_VOLTAGE_NUM 0x40
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enum {
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BD718XX_BUCK1 = 0,
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BD718XX_BUCK2,
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BD718XX_BUCK3,
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BD718XX_BUCK4,
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BD718XX_BUCK5,
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BD718XX_BUCK6,
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BD718XX_BUCK7,
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BD718XX_BUCK8,
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BD718XX_LDO1,
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BD718XX_LDO2,
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BD718XX_LDO3,
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BD718XX_LDO4,
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BD718XX_LDO5,
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BD718XX_LDO6,
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BD718XX_LDO7,
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BD718XX_REGULATOR_AMOUNT,
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};
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#define BD71837_BUCK5_VOLTAGE_NUM 0x08
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/* Common voltage configurations
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*
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* Note, we support only one range of voltages for each buck/LDO until we
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* get pickable ranges support. (See range selection bits for BUCK5 and
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* LDO1. On BD71847 also the second no DVS buck and LDO5)
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*/
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#define BD718XX_DVS_BUCK_VOLTAGE_NUM 0x3D
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#define BD718XX_1ST_NODVS_BUCK_VOLTAGE_NUM 0x08
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#define BD71837_4TH_NODVS_BUCK_VOLTAGE_NUM 0x3D
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#define BD718XX_LDO1_VOLTAGE_NUM 0x04
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#define BD718XX_LDO2_VOLTAGE_NUM 0x02
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#define BD718XX_LDO3_VOLTAGE_NUM 0x10
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#define BD718XX_LDO4_VOLTAGE_NUM 0x0A
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#define BD718XX_LDO5_VOLTAGE_NUM 0x10
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#define BD718XX_LDO6_VOLTAGE_NUM 0x0A
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/* BD71837 specific voltage configurations */
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#define BD71837_BUCK6_VOLTAGE_NUM 0x04
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#define BD71837_BUCK7_VOLTAGE_NUM 0x08
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#define BD71837_BUCK8_VOLTAGE_NUM 0x40
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#define BD71837_LDO1_VOLTAGE_NUM 0x04
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#define BD71837_LDO2_VOLTAGE_NUM 0x02
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#define BD71837_LDO3_VOLTAGE_NUM 0x10
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#define BD71837_LDO4_VOLTAGE_NUM 0x10
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#define BD71837_LDO5_VOLTAGE_NUM 0x10
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#define BD71837_LDO6_VOLTAGE_NUM 0x10
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#define BD71837_LDO7_VOLTAGE_NUM 0x10
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/* BD71847 specific voltage configurations */
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#define BD71847_BUCK4_VOLTAGE_NUM 0x04
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/* Registers specific to BD71837 */
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enum {
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BD71837_REG_REV = 0x00,
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BD71837_REG_SWRESET = 0x01,
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BD71837_REG_I2C_DEV = 0x02,
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BD71837_REG_PWRCTRL0 = 0x03,
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BD71837_REG_PWRCTRL1 = 0x04,
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BD71837_REG_BUCK1_CTRL = 0x05,
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BD71837_REG_BUCK2_CTRL = 0x06,
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK5_CTRL = 0x09,
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BD71837_REG_BUCK6_CTRL = 0x0A,
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BD71837_REG_BUCK7_CTRL = 0x0B,
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BD71837_REG_BUCK8_CTRL = 0x0C,
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BD71837_REG_BUCK1_VOLT_RUN = 0x0D,
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BD71837_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD71837_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD71837_REG_BUCK2_VOLT_RUN = 0x10,
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BD71837_REG_BUCK2_VOLT_IDLE = 0x11,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_BUCK5_VOLT = 0x14,
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BD71837_REG_BUCK6_VOLT = 0x15,
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BD71837_REG_BUCK7_VOLT = 0x16,
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BD71837_REG_BUCK8_VOLT = 0x17,
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BD71837_REG_LDO1_VOLT = 0x18,
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BD71837_REG_LDO2_VOLT = 0x19,
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BD71837_REG_LDO3_VOLT = 0x1A,
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BD71837_REG_LDO4_VOLT = 0x1B,
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BD71837_REG_LDO5_VOLT = 0x1C,
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BD71837_REG_LDO6_VOLT = 0x1D,
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BD71837_REG_LDO7_VOLT = 0x1E,
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BD71837_REG_TRANS_COND0 = 0x1F,
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BD71837_REG_TRANS_COND1 = 0x20,
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BD71837_REG_VRFAULTEN = 0x21,
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BD718XX_REG_MVRFLTMASK0 = 0x22,
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BD718XX_REG_MVRFLTMASK1 = 0x23,
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BD718XX_REG_MVRFLTMASK2 = 0x24,
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BD71837_REG_RCVCFG = 0x25,
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BD71837_REG_RCVNUM = 0x26,
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BD71837_REG_PWRONCONFIG0 = 0x27,
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BD71837_REG_PWRONCONFIG1 = 0x28,
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BD71837_REG_RESETSRC = 0x29,
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BD71837_REG_MIRQ = 0x2A,
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BD71837_REG_IRQ = 0x2B,
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BD71837_REG_IN_MON = 0x2C,
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BD71837_REG_POW_STATE = 0x2D,
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BD71837_REG_OUT32K = 0x2E,
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BD71837_REG_REGLOCK = 0x2F,
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BD71837_REG_OTPVER = 0xFF,
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BD71837_MAX_REGISTER = 0x100,
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_LDO7_VOLT = 0x1E,
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};
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/* Registers common for BD71837 and BD71847 */
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enum {
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BD718XX_REG_REV = 0x00,
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BD718XX_REG_SWRESET = 0x01,
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BD718XX_REG_I2C_DEV = 0x02,
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BD718XX_REG_PWRCTRL0 = 0x03,
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BD718XX_REG_PWRCTRL1 = 0x04,
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BD718XX_REG_BUCK1_CTRL = 0x05,
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BD718XX_REG_BUCK2_CTRL = 0x06,
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BD718XX_REG_1ST_NODVS_BUCK_CTRL = 0x09,
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BD718XX_REG_2ND_NODVS_BUCK_CTRL = 0x0A,
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BD718XX_REG_3RD_NODVS_BUCK_CTRL = 0x0B,
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BD718XX_REG_4TH_NODVS_BUCK_CTRL = 0x0C,
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BD718XX_REG_BUCK1_VOLT_RUN = 0x0D,
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BD718XX_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD718XX_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD718XX_REG_BUCK2_VOLT_RUN = 0x10,
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BD718XX_REG_BUCK2_VOLT_IDLE = 0x11,
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BD718XX_REG_1ST_NODVS_BUCK_VOLT = 0x14,
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BD718XX_REG_2ND_NODVS_BUCK_VOLT = 0x15,
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BD718XX_REG_3RD_NODVS_BUCK_VOLT = 0x16,
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BD718XX_REG_4TH_NODVS_BUCK_VOLT = 0x17,
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BD718XX_REG_LDO1_VOLT = 0x18,
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BD718XX_REG_LDO2_VOLT = 0x19,
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BD718XX_REG_LDO3_VOLT = 0x1A,
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BD718XX_REG_LDO4_VOLT = 0x1B,
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BD718XX_REG_LDO5_VOLT = 0x1C,
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BD718XX_REG_LDO6_VOLT = 0x1D,
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BD718XX_REG_TRANS_COND0 = 0x1F,
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BD718XX_REG_TRANS_COND1 = 0x20,
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BD718XX_REG_VRFAULTEN = 0x21,
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BD718XX_REG_MVRFLTMASK0 = 0x22,
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BD718XX_REG_MVRFLTMASK1 = 0x23,
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BD718XX_REG_MVRFLTMASK2 = 0x24,
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BD718XX_REG_RCVCFG = 0x25,
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BD718XX_REG_RCVNUM = 0x26,
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BD718XX_REG_PWRONCONFIG0 = 0x27,
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BD718XX_REG_PWRONCONFIG1 = 0x28,
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BD718XX_REG_RESETSRC = 0x29,
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BD718XX_REG_MIRQ = 0x2A,
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BD718XX_REG_IRQ = 0x2B,
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BD718XX_REG_IN_MON = 0x2C,
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BD718XX_REG_POW_STATE = 0x2D,
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BD718XX_REG_OUT32K = 0x2E,
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BD718XX_REG_REGLOCK = 0x2F,
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BD718XX_REG_OTPVER = 0xFF,
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BD718XX_MAX_REGISTER = 0x100,
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};
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#define REGLOCK_PWRSEQ 0x1
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#define REGLOCK_VREG 0x10
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/* Generic BUCK control masks */
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#define BD71837_BUCK_SEL 0x02
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#define BD71837_BUCK_EN 0x01
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#define BD71837_BUCK_RUN_ON 0x04
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#define BD718XX_BUCK_SEL 0x02
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#define BD718XX_BUCK_EN 0x01
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#define BD718XX_BUCK_RUN_ON 0x04
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/* Generic LDO masks */
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#define BD71837_LDO_SEL 0x80
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#define BD71837_LDO_EN 0x40
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#define BD718XX_LDO_SEL 0x80
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#define BD718XX_LDO_EN 0x40
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/* BD71837 BUCK ramp rate CTRL reg bits */
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#define BUCK_RAMPRATE_MASK 0xC0
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@@ -115,49 +134,27 @@ enum {
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#define BUCK_RAMPRATE_2P50MV 0x2
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#define BUCK_RAMPRATE_1P25MV 0x3
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/* BD71837_REG_BUCK1_VOLT_RUN bits */
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#define BUCK1_RUN_MASK 0x3F
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#define BUCK1_RUN_DEFAULT 0x14
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#define DVS_BUCK_RUN_MASK 0x3F
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#define DVS_BUCK_SUSP_MASK 0x3F
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#define DVS_BUCK_IDLE_MASK 0x3F
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/* BD71837_REG_BUCK1_VOLT_SUSP bits */
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#define BUCK1_SUSP_MASK 0x3F
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#define BUCK1_SUSP_DEFAULT 0x14
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#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
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#define BD71847_BUCK4_MASK 0x03
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#define BD71837_BUCK6_MASK 0x03
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#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
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#define BD718XX_4TH_NODVS_BUCK_MASK 0x3F
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/* BD71837_REG_BUCK1_VOLT_IDLE bits */
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#define BUCK1_IDLE_MASK 0x3F
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#define BUCK1_IDLE_DEFAULT 0x14
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#define BD718XX_LDO1_MASK 0x03
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#define BD718XX_LDO2_MASK 0x20
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#define BD718XX_LDO3_MASK 0x0F
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#define BD718XX_LDO4_MASK 0x0F
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#define BD718XX_LDO6_MASK 0x0F
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/* BD71837_REG_BUCK2_VOLT_RUN bits */
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#define BUCK2_RUN_MASK 0x3F
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#define BUCK2_RUN_DEFAULT 0x1E
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#define BD71837_LDO5_MASK 0x0F
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#define BD71847_LDO5_MASK 0x0F
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/* BD71837_REG_BUCK2_VOLT_IDLE bits */
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#define BUCK2_IDLE_MASK 0x3F
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#define BUCK2_IDLE_DEFAULT 0x14
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#define BD71837_LDO7_MASK 0x0F
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/* BD71837_REG_BUCK3_VOLT_RUN bits */
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#define BUCK3_RUN_MASK 0x3F
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#define BUCK3_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK4_VOLT_RUN bits */
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#define BUCK4_RUN_MASK 0x3F
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#define BUCK4_RUN_DEFAULT 0x1E
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/* BD71837_REG_BUCK5_VOLT bits */
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#define BUCK5_MASK 0x07
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#define BUCK5_DEFAULT 0x02
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/* BD71837_REG_BUCK6_VOLT bits */
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#define BUCK6_MASK 0x03
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#define BUCK6_DEFAULT 0x03
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/* BD71837_REG_BUCK7_VOLT bits */
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#define BUCK7_MASK 0x07
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#define BUCK7_DEFAULT 0x03
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/* BD71837_REG_BUCK8_VOLT bits */
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#define BUCK8_MASK 0x3F
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#define BUCK8_DEFAULT 0x1E
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/* BD718XX Voltage monitoring masks */
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#define BD718XX_BUCK1_VRMON80 0x1
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@@ -221,27 +218,6 @@ enum {
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#define BD71837_INT_ON_REQ_MASK 0x2
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#define BD71837_INT_STBY_REQ_MASK 0x1
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/* BD71837_REG_LDO1_VOLT bits */
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#define LDO1_MASK 0x03
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/* BD71837_REG_LDO1_VOLT bits */
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#define LDO2_MASK 0x20
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/* BD71837_REG_LDO3_VOLT bits */
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#define LDO3_MASK 0x0F
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/* BD71837_REG_LDO4_VOLT bits */
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#define LDO4_MASK 0x0F
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/* BD71837_REG_LDO5_VOLT bits */
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#define LDO5_MASK 0x0F
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/* BD71837_REG_LDO6_VOLT bits */
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#define LDO6_MASK 0x0F
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/* BD71837_REG_LDO7_VOLT bits */
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#define LDO7_MASK 0x0F
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/* Register write induced reset settings */
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/*
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@@ -341,10 +317,11 @@ enum {
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BD718XX_PWRBTN_LONG_PRESS_15S
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};
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struct bd71837_pmic;
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struct bd71837_clk;
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struct bd718xx_pmic;
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struct bd718xx_clk;
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struct bd71837 {
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unsigned int chip_type;
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struct device *dev;
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struct regmap *regmap;
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unsigned long int id;
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@@ -352,8 +329,8 @@ struct bd71837 {
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int chip_irq;
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struct regmap_irq_chip_data *irq_data;
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struct bd71837_pmic *pmic;
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struct bd71837_clk *clk;
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struct bd718xx_pmic *pmic;
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struct bd718xx_clk *clk;
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};
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#endif /* __LINUX_MFD_BD71837_H__ */
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