drm/radeon/kms: add support for CP setup on SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
committed by
Dave Airlie
Dave Airlie
parent
8b074dd640
commit
48c0c902e2
@@ -31,6 +31,7 @@
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#include "radeon_drm.h"
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#include "sid.h"
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#include "atom.h"
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#include "si_blit_shaders.h"
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#define SI_PFP_UCODE_SIZE 2144
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#define SI_PM4_UCODE_SIZE 2144
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@@ -1861,6 +1862,272 @@ static void si_gpu_init(struct radeon_device *rdev)
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udelay(50);
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}
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/*
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* CP.
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*/
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static void si_cp_enable(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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else {
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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WREG32(SCRATCH_UMSK, 0);
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}
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udelay(50);
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}
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static int si_cp_load_microcode(struct radeon_device *rdev)
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{
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const __be32 *fw_data;
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int i;
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if (!rdev->me_fw || !rdev->pfp_fw)
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return -EINVAL;
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si_cp_enable(rdev, false);
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/* PFP */
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fw_data = (const __be32 *)rdev->pfp_fw->data;
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WREG32(CP_PFP_UCODE_ADDR, 0);
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for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
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WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_PFP_UCODE_ADDR, 0);
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/* CE */
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fw_data = (const __be32 *)rdev->ce_fw->data;
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WREG32(CP_CE_UCODE_ADDR, 0);
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for (i = 0; i < SI_CE_UCODE_SIZE; i++)
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WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_CE_UCODE_ADDR, 0);
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/* ME */
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fw_data = (const __be32 *)rdev->me_fw->data;
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WREG32(CP_ME_RAM_WADDR, 0);
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for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
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WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
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WREG32(CP_ME_RAM_WADDR, 0);
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WREG32(CP_PFP_UCODE_ADDR, 0);
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WREG32(CP_CE_UCODE_ADDR, 0);
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WREG32(CP_ME_RAM_WADDR, 0);
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WREG32(CP_ME_RAM_RADDR, 0);
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return 0;
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}
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static int si_cp_start(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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int r, i;
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r = radeon_ring_lock(rdev, ring, 7 + 4);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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/* init the CP */
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radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
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radeon_ring_write(ring, 0x1);
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radeon_ring_write(ring, 0x0);
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radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
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radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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/* init the CE partitions */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
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radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0xe000);
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radeon_ring_unlock_commit(rdev, ring);
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si_cp_enable(rdev, true);
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r = radeon_ring_lock(rdev, ring, si_default_size + 10);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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/* setup clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
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for (i = 0; i < si_default_size; i++)
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radeon_ring_write(ring, si_default_state[i]);
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
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/* set clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, 0x00000316);
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radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
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radeon_ring_unlock_commit(rdev, ring);
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for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
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ring = &rdev->ring[i];
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r = radeon_ring_lock(rdev, ring, 2);
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/* clear the compute context state */
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radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(ring, 0);
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radeon_ring_unlock_commit(rdev, ring);
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}
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return 0;
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}
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static void si_cp_fini(struct radeon_device *rdev)
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{
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si_cp_enable(rdev, false);
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radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
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}
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static int si_cp_resume(struct radeon_device *rdev)
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{
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struct radeon_ring *ring;
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u32 tmp;
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u32 rb_bufsz;
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int r;
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/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
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WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
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SOFT_RESET_PA |
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SOFT_RESET_VGT |
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SOFT_RESET_SPI |
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SOFT_RESET_SX));
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RREG32(GRBM_SOFT_RESET);
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mdelay(15);
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WREG32(GRBM_SOFT_RESET, 0);
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RREG32(GRBM_SOFT_RESET);
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WREG32(CP_SEM_WAIT_TIMER, 0x0);
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WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
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/* Set the write pointer delay */
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WREG32(CP_RB_WPTR_DELAY, 0);
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WREG32(CP_DEBUG, 0);
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WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
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/* ring 0 - compute and gfx */
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/* Set ring buffer size */
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ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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rb_bufsz = drm_order(ring->ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB0_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
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ring->wptr = 0;
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WREG32(CP_RB0_WPTR, ring->wptr);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
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if (rdev->wb.enabled)
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WREG32(SCRATCH_UMSK, 0xff);
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else {
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tmp |= RB_NO_UPDATE;
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WREG32(SCRATCH_UMSK, 0);
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}
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mdelay(1);
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WREG32(CP_RB0_CNTL, tmp);
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WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
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ring->rptr = RREG32(CP_RB0_RPTR);
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/* ring1 - compute only */
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/* Set ring buffer size */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
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rb_bufsz = drm_order(ring->ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB1_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
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ring->wptr = 0;
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WREG32(CP_RB1_WPTR, ring->wptr);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
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mdelay(1);
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WREG32(CP_RB1_CNTL, tmp);
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WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
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ring->rptr = RREG32(CP_RB1_RPTR);
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/* ring2 - compute only */
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/* Set ring buffer size */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
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rb_bufsz = drm_order(ring->ring_size / 8);
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tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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#ifdef __BIG_ENDIAN
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tmp |= BUF_SWAP_32BIT;
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#endif
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WREG32(CP_RB2_CNTL, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
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ring->wptr = 0;
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WREG32(CP_RB2_WPTR, ring->wptr);
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/* set the wb address wether it's enabled or not */
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WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
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WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
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mdelay(1);
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WREG32(CP_RB2_CNTL, tmp);
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WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
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ring->rptr = RREG32(CP_RB2_RPTR);
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/* start the rings */
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si_cp_start(rdev);
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
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r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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if (r) {
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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return r;
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}
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r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
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if (r) {
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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}
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r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
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if (r) {
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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}
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return 0;
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}
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bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 srbm_status;
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