Merge branch 'core/locking' into tracing/ftrace
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@@ -138,7 +138,8 @@ do { \
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__instruction_hazard(); \
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} while (0)
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
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defined(CONFIG_CPU_R5500)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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@@ -26,7 +26,7 @@
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* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
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* current versions due to erratum G105.
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*
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* VR7701 only implements the Load prefetch.
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* VR5500 (including VR5701 and VR7701) only implement load prefetch.
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*
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* Finally MIPS32 and MIPS64 implement all of the following hints.
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*/
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