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drm/radeon: restructure cg/pg on cik (v2)

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- use new cg/pg flags for finer grained clock and
powergating control
- restructure the cg/pg code so it can be called from
other components such as dpm

v2: fix build breakage from rebase

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2013-08-09 11:18:39 -04:00
parent ca6ebb39df
commit 473359bc28
3 changed files with 170 additions and 69 deletions
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drivers/gpu/drm/radeon/cikd.h
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@@ -285,6 +285,7 @@
#define PCIE_CNTL2 0x1001001c /* PCIE */
# define SLV_MEM_LS_EN (1 << 16)
# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
# define MST_MEM_LS_EN (1 << 18)
# define REPLAY_MEM_LS_EN (1 << 19)