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dmaengine: omap-dma: consolidate clearing channel status register

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Consolidate clearing of the channel status register, rather than open
coding the same functionality in two places.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2013-11-02 21:23:06 +00:00
parent 49ae0b2943
commit 470b23f730
1 changed files with 10 additions and 10 deletions
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20
drivers/dma/omap-dma.c
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@@ -169,6 +169,14 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
kfree(container_of(vd, struct omap_desc, vd)); kfree(container_of(vd, struct omap_desc, vd));
} }
static void omap_dma_clear_csr(struct omap_chan *c)
{
if (dma_omap1())
c->plat->dma_read(CSR, c->dma_ch);
else
c->plat->dma_write(~0, CSR, c->dma_ch);
}
static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
{ {
struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
@@ -191,11 +199,7 @@ static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) } else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch); c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
/* Clear CSR */ omap_dma_clear_csr(c);
if (dma_omap1())
c->plat->dma_read(CSR, c->dma_ch);
else
c->plat->dma_write(~0, CSR, c->dma_ch);
/* Enable interrupts */ /* Enable interrupts */
c->plat->dma_write(d->cicr, CICR, c->dma_ch); c->plat->dma_write(d->cicr, CICR, c->dma_ch);
@@ -214,11 +218,7 @@ static void omap_dma_stop(struct omap_chan *c)
/* disable irq */ /* disable irq */
c->plat->dma_write(0, CICR, c->dma_ch); c->plat->dma_write(0, CICR, c->dma_ch);
/* Clear CSR */ omap_dma_clear_csr(c);
if (dma_omap1())
c->plat->dma_read(CSR, c->dma_ch);
else
c->plat->dma_write(~0, CSR, c->dma_ch);
val = c->plat->dma_read(CCR, c->dma_ch); val = c->plat->dma_read(CCR, c->dma_ch);
if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {