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drm/amdgpu: define soc15_ras_field_entry for reuse

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The struct soc15_ras_field_entry will be reused by
other IPs, such as mmhub and gc

v2: rename ras_subblock_regs to gc_ras_fields_vg20,
because the future asic maybe have a different table.

Signed-off-by: Dennis Li <dennis.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dennis Li
2019-11-19 16:25:25 +08:00
committed by Alex Deucher
parent d98a07aea6
commit 46f719696e
2 changed files with 23 additions and 23 deletions
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12
drivers/gpu/drm/amd/amdgpu/soc15.h
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@@ -60,6 +60,18 @@ struct soc15_allowed_register_entry {
bool grbm_indexed;
};
struct soc15_ras_field_entry {
const char *name;
uint32_t hwip;
uint32_t inst;
uint32_t seg;
uint32_t reg_offset;
uint32_t sec_count_mask;
uint32_t sec_count_shift;
uint32_t ded_count_mask;
uint32_t ded_count_shift;
};
#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)