xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915/vgpu: Disallow loading on old vGPU hosts

Browse Source 
Since commit fd8526e509 ("drm/i915/execlists: Trust the CSB") we
actually broke the force-mmio mode for our execlists implementation. No
one noticed, so ergo no one is actually using an old vGPU host (where we
required the older method) and so can simply remove the broken support.

v2: csb_read can go as well (Mika)

Reported-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Fixes: fd8526e509 ("drm/i915/execlists: Trust the CSB")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130125954.11924-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
2018-11-30 12:59:54 +00:00
parent 26af893184
commit 46592892e1
3 changed files with 22 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/drm/i915/intel_ringbuffer.h
View File

@@ -312,13 +312,6 @@ struct intel_engine_execlists {
*/
struct rb_root_cached queue;
/**
* @csb_read: control register for Context Switch buffer
*
* Note this register is always in mmio.
*/
u32 __iomem *csb_read;
/**
* @csb_write: control register for Context Switch buffer
*
@@ -338,15 +331,6 @@ struct intel_engine_execlists {
*/
u32 preempt_complete_status;
/**
* @csb_write_reset: reset value for CSB write pointer
*
* As the CSB write pointer maybe either in HWSP or as a field
* inside an mmio register, we want to reprogram it slightly
* differently to avoid later confusion.
*/
u32 csb_write_reset;
/**
* @csb_head: context status buffer head
*/