ARM: dts: omap5: add clkctrl nodes
Add clkctrl nodes for OMAP5 SoC. These are going to be acting as replacement for part of the existing clock data and the existing clkctrl hooks under hwmod data. This patch also removes any obsolete clock nodes, and reroutes all users for these to use the new clkctrl clocks instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tero Kristo
committato da
Tony Lindgren
Tony Lindgren
parent
a5c82a09d8
commit
460c49610d
@@ -432,22 +432,6 @@
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reg = <0x0528>;
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};
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dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
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reg = <0x0538>;
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};
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dmic_gfclk: dmic_gfclk@538 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
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ti,bit-shift = <24>;
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reg = <0x0538>;
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};
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mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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@@ -464,86 +448,6 @@
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reg = <0x0540>;
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};
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mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
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reg = <0x0548>;
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};
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mcbsp1_gfclk: mcbsp1_gfclk@548 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
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ti,bit-shift = <24>;
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reg = <0x0548>;
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};
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mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
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reg = <0x0550>;
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};
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mcbsp2_gfclk: mcbsp2_gfclk@550 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
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ti,bit-shift = <24>;
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reg = <0x0550>;
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};
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mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
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reg = <0x0558>;
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};
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mcbsp3_gfclk: mcbsp3_gfclk@558 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
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ti,bit-shift = <24>;
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reg = <0x0558>;
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};
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timer5_gfclk_mux: timer5_gfclk_mux@568 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x0568>;
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};
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timer6_gfclk_mux: timer6_gfclk_mux@570 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x0570>;
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};
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timer7_gfclk_mux: timer7_gfclk_mux@578 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x0578>;
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};
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timer8_gfclk_mux: timer8_gfclk_mux@580 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x0580>;
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};
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dummy_ck: dummy_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -603,23 +507,8 @@
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clock-mult = <1>;
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clock-div = <1>;
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};
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gpio1_dbclk: gpio1_dbclk@1938 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1938>;
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};
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timer1_gfclk_mux: timer1_gfclk_mux@1940 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x1940>;
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};
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};
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&cm_core_clocks {
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dpll_per_byp_mux: dpll_per_byp_mux@14c {
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@@ -825,95 +714,6 @@
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ti,dividers = <1>, <8>;
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};
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dss_32khz_clk: dss_32khz_clk@1420 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <11>;
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reg = <0x1420>;
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};
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dss_48mhz_clk: dss_48mhz_clk@1420 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&func_48m_fclk>;
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ti,bit-shift = <9>;
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reg = <0x1420>;
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};
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dss_dss_clk: dss_dss_clk@1420 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_per_h12x2_ck>;
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ti,bit-shift = <8>;
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reg = <0x1420>;
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ti,set-rate-parent;
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};
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dss_sys_clk: dss_sys_clk@1420 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dss_syc_gfclk_div>;
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ti,bit-shift = <10>;
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reg = <0x1420>;
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};
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gpio2_dbclk: gpio2_dbclk@1060 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1060>;
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};
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gpio3_dbclk: gpio3_dbclk@1068 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1068>;
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};
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gpio4_dbclk: gpio4_dbclk@1070 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1070>;
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};
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gpio5_dbclk: gpio5_dbclk@1078 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1078>;
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};
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gpio6_dbclk: gpio6_dbclk@1080 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1080>;
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};
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gpio7_dbclk: gpio7_dbclk@1110 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1110>;
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};
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gpio8_dbclk: gpio8_dbclk@1118 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1118>;
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};
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iss_ctrlclk: iss_ctrlclk@1320 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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@@ -938,118 +738,6 @@
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reg = <0x0f20>;
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};
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mmc1_32khz_clk: mmc1_32khz_clk@1628 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_32k_ck>;
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ti,bit-shift = <8>;
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reg = <0x1628>;
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};
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sata_ref_clk: sata_ref_clk@1688 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_clkin>;
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ti,bit-shift = <8>;
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reg = <0x1688>;
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};
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usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_usb_m2_ck>;
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ti,bit-shift = <13>;
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reg = <0x1658>;
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};
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usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_usb_m2_ck>;
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ti,bit-shift = <14>;
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reg = <0x1658>;
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};
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usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_usb_m2_ck>;
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ti,bit-shift = <7>;
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reg = <0x1658>;
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};
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usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <11>;
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reg = <0x1658>;
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};
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usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <12>;
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reg = <0x1658>;
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};
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usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <6>;
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reg = <0x1658>;
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};
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utmi_p1_gfclk: utmi_p1_gfclk@1658 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
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ti,bit-shift = <24>;
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reg = <0x1658>;
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};
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usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&utmi_p1_gfclk>;
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ti,bit-shift = <8>;
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reg = <0x1658>;
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};
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utmi_p2_gfclk: utmi_p2_gfclk@1658 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
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ti,bit-shift = <25>;
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reg = <0x1658>;
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};
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usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&utmi_p2_gfclk>;
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ti,bit-shift = <9>;
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reg = <0x1658>;
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};
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usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <10>;
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reg = <0x1658>;
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};
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usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_usb_clkdcoldo>;
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ti,bit-shift = <8>;
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reg = <0x16f0>;
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};
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usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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@@ -1058,30 +746,6 @@
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reg = <0x0640>;
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};
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usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <8>;
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reg = <0x1668>;
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};
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usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <9>;
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reg = <0x1668>;
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};
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usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3init_60m_fclk>;
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ti,bit-shift = <10>;
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reg = <0x1668>;
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};
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fdif_fclk: fdif_fclk@1328 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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@@ -1115,88 +779,6 @@
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ti,max-div = <2>;
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reg = <0x1638>;
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};
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mmc1_fclk_mux: mmc1_fclk_mux@1628 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
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ti,bit-shift = <24>;
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reg = <0x1628>;
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};
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mmc1_fclk: mmc1_fclk@1628 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&mmc1_fclk_mux>;
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ti,bit-shift = <25>;
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ti,max-div = <2>;
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reg = <0x1628>;
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};
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mmc2_fclk_mux: mmc2_fclk_mux@1630 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
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ti,bit-shift = <24>;
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reg = <0x1630>;
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};
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mmc2_fclk: mmc2_fclk@1630 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&mmc2_fclk_mux>;
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ti,bit-shift = <25>;
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ti,max-div = <2>;
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reg = <0x1630>;
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};
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timer10_gfclk_mux: timer10_gfclk_mux@1028 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x1028>;
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};
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timer11_gfclk_mux: timer11_gfclk_mux@1030 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x1030>;
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};
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timer2_gfclk_mux: timer2_gfclk_mux@1038 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin>, <&sys_32k_ck>;
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ti,bit-shift = <24>;
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reg = <0x1038>;
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};
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|
||||
timer3_gfclk_mux: timer3_gfclk_mux@1040 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x1040>;
|
||||
};
|
||||
|
||||
timer4_gfclk_mux: timer4_gfclk_mux@1048 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x1048>;
|
||||
};
|
||||
|
||||
timer9_gfclk_mux: timer9_gfclk_mux@1050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x1050>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_core_clockdomains {
|
||||
@@ -1394,3 +976,206 @@
|
||||
reg = <0x021c>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_core_aon {
|
||||
mpu_cm: mpu_cm@300 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x300 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x300 0x100>;
|
||||
|
||||
mpu_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp_cm: dsp_cm@400 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x400 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x400 0x100>;
|
||||
|
||||
dsp_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
abe_cm: abe_cm@500 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x500 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x500 0x100>;
|
||||
|
||||
abe_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x64>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&cm_core {
|
||||
l3main1_cm: l3main1_cm@700 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x700 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x700 0x100>;
|
||||
|
||||
l3main1_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l3main2_cm: l3main2_cm@800 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x800 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x800 0x100>;
|
||||
|
||||
l3main2_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_cm: ipu_cm@900 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x900 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x900 0x100>;
|
||||
|
||||
ipu_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma_cm: dma_cm@a00 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0xa00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xa00 0x100>;
|
||||
|
||||
dma_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
emif_cm: emif_cm@b00 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0xb00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xb00 0x100>;
|
||||
|
||||
emif_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x1c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l4cfg_cm: l4cfg_cm@d00 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0xd00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xd00 0x100>;
|
||||
|
||||
l4cfg_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x14>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l3instr_cm: l3instr_cm@e00 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0xe00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xe00 0x100>;
|
||||
|
||||
l3instr_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0xc>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l4per_cm: l4per_cm@1000 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1000 0x200>;
|
||||
|
||||
l4per_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x15c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dss_cm: dss_cm@1400 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1400 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1400 0x100>;
|
||||
|
||||
dss_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
l3init_cm: l3init_cm@1600 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1600 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1600 0x100>;
|
||||
|
||||
l3init_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0xd4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&prm {
|
||||
wkupaon_cm: wkupaon_cm@1900 {
|
||||
compatible = "ti,omap4-cm";
|
||||
reg = <0x1900 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1900 0x100>;
|
||||
|
||||
wkupaon_clkctrl: clk@20 {
|
||||
compatible = "ti,clkctrl";
|
||||
reg = <0x20 0x5c>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Fai riferimento in un nuovo problema
Block a user