RDMA/mlx5: Refactor mlx5_ib_alloc_ucontext() response
Refactor mlx5_ib_alloc_ucontext() to set its response fields in a cleaner way. It includes, - Move the relevant code to a self contained function. - Calculate the response length once and drop redundant code all around. - Reuse previously set ucontext fields once preparing the response. The self contained function will be used in next patch as part of implementing the query ucontext functionality. Link: https://lore.kernel.org/r/20200630093916.332097-5-leon@kernel.org Signed-off-by: Yishai Hadas <yishaih@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Yishai Hadas
committed by
Jason Gunthorpe
Jason Gunthorpe
parent
1c8fb1ea5a
commit
45ec21c971
@@ -1765,6 +1765,92 @@ static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
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mlx5_ib_disable_lb(dev, true, false);
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}
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static int set_ucontext_resp(struct ib_ucontext *uctx,
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struct mlx5_ib_alloc_ucontext_resp *resp)
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{
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struct ib_device *ibdev = uctx->device;
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struct mlx5_ib_dev *dev = to_mdev(ibdev);
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struct mlx5_ib_ucontext *context = to_mucontext(uctx);
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struct mlx5_bfreg_info *bfregi = &context->bfregi;
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int err;
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if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
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err = mlx5_cmd_dump_fill_mkey(dev->mdev,
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&resp->dump_fill_mkey);
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if (err)
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return err;
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resp->comp_mask |=
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
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}
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resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
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if (dev->wc_support)
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resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
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log_bf_reg_size);
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resp->cache_line_size = cache_line_size();
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resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
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resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
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resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
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resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
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resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
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resp->cqe_version = context->cqe_version;
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resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
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MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
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resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
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MLX5_CAP_GEN(dev->mdev,
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num_of_uars_per_page) : 1;
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if (mlx5_accel_ipsec_device_caps(dev->mdev) &
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MLX5_ACCEL_IPSEC_CAP_DEVICE) {
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if (mlx5_get_flow_namespace(dev->mdev,
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MLX5_FLOW_NAMESPACE_EGRESS))
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resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
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if (mlx5_accel_ipsec_device_caps(dev->mdev) &
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MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
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resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
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if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
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resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
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if (mlx5_accel_ipsec_device_caps(dev->mdev) &
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MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
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resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
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/* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
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}
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resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
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bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
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resp->num_ports = dev->num_ports;
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resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
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MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
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if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
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mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
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resp->eth_min_inline++;
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}
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if (dev->mdev->clock_info)
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resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
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/*
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* We don't want to expose information from the PCI bar that is located
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* after 4096 bytes, so if the arch only supports larger pages, let's
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* pretend we don't support reading the HCA's core clock. This is also
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* forced by mmap function.
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*/
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if (PAGE_SIZE <= 4096) {
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resp->comp_mask |=
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
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resp->hca_core_clock_offset =
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offsetof(struct mlx5_init_seg,
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internal_timer_h) % PAGE_SIZE;
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}
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if (MLX5_CAP_GEN(dev->mdev, ece_support))
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resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
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resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
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return 0;
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}
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static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
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struct ib_udata *udata)
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{
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@@ -1772,14 +1858,12 @@ static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
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struct mlx5_ib_dev *dev = to_mdev(ibdev);
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struct mlx5_ib_alloc_ucontext_req_v2 req = {};
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struct mlx5_ib_alloc_ucontext_resp resp = {};
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struct mlx5_core_dev *mdev = dev->mdev;
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struct mlx5_ib_ucontext *context = to_mucontext(uctx);
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struct mlx5_bfreg_info *bfregi;
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int ver;
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int err;
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size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
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max_cqe_version);
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u32 dump_fill_mkey;
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bool lib_uar_4k;
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bool lib_uar_dyn;
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@@ -1808,37 +1892,6 @@ static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
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if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
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return -EINVAL;
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resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
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if (dev->wc_support)
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resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
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resp.cache_line_size = cache_line_size();
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resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
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resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
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resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
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resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
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resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
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resp.cqe_version = min_t(__u8,
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(__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
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req.max_cqe_version);
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resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
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MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
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resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
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MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
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resp.response_length = min(offsetof(typeof(resp), response_length) +
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sizeof(resp.response_length), udata->outlen);
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if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
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if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
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resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
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if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
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resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
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if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
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resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
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if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
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resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
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/* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
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}
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lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
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lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
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bfregi = &context->bfregi;
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@@ -1887,87 +1940,24 @@ uar_done:
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if (err)
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goto out_devx;
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if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
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err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
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if (err)
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goto out_mdev;
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}
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INIT_LIST_HEAD(&context->db_page_list);
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mutex_init(&context->db_page_mutex);
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resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs;
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resp.num_ports = dev->num_ports;
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context->cqe_version = min_t(__u8,
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(__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
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req.max_cqe_version);
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if (offsetofend(typeof(resp), cqe_version) <= udata->outlen)
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resp.response_length += sizeof(resp.cqe_version);
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if (offsetofend(typeof(resp), cmds_supp_uhw) <= udata->outlen) {
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resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
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MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
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resp.response_length += sizeof(resp.cmds_supp_uhw);
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}
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if (offsetofend(typeof(resp), eth_min_inline) <= udata->outlen) {
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if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
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mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
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resp.eth_min_inline++;
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}
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resp.response_length += sizeof(resp.eth_min_inline);
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}
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if (offsetofend(typeof(resp), clock_info_versions) <= udata->outlen) {
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if (mdev->clock_info)
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resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
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resp.response_length += sizeof(resp.clock_info_versions);
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}
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/*
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* We don't want to expose information from the PCI bar that is located
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* after 4096 bytes, so if the arch only supports larger pages, let's
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* pretend we don't support reading the HCA's core clock. This is also
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* forced by mmap function.
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*/
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if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) {
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if (PAGE_SIZE <= 4096) {
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resp.comp_mask |=
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
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resp.hca_core_clock_offset =
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offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
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}
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resp.response_length += sizeof(resp.hca_core_clock_offset);
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}
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if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen)
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resp.response_length += sizeof(resp.log_uar_size);
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if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen)
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resp.response_length += sizeof(resp.num_uars_per_page);
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if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) {
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resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
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resp.response_length += sizeof(resp.num_dyn_bfregs);
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}
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if (offsetofend(typeof(resp), dump_fill_mkey) <= udata->outlen) {
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if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
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resp.dump_fill_mkey = dump_fill_mkey;
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resp.comp_mask |=
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
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}
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resp.response_length += sizeof(resp.dump_fill_mkey);
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}
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if (MLX5_CAP_GEN(dev->mdev, ece_support))
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resp.comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
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err = set_ucontext_resp(uctx, &resp);
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if (err)
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goto out_mdev;
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resp.response_length = min(udata->outlen, sizeof(resp));
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err = ib_copy_to_udata(udata, &resp, resp.response_length);
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if (err)
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goto out_mdev;
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bfregi->ver = ver;
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bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
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context->cqe_version = resp.cqe_version;
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context->lib_caps = req.lib_caps;
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print_lib_caps(dev, context->lib_caps);
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