drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform
[ Upstream commit b3dc549986eb7b38eba4a144e979dc93f386751f ] Due to high latency in PCIE clock switching on RKL platforms, switching the PCIE clock dynamically at runtime can lead to HDMI/DP audio problems. On newer asics this is handled in the SMU firmware. For SMU7-based asics, disable PCIE clock switching to avoid the issue. AMD provide a parameter to disable PICE_DPM. modprobe amdgpu ppfeaturemask=0xfff7bffb It's better to contorl PCIE_DPM in amd gpu driver, switch PCI_DPM by determining intel RKL platform for SMU7-based asics. Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issue") Ref: https://lists.freedesktop.org/archives/amd-gfx/2021-August/067413.html Signed-off-by: Koba Ko <koba.ko@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:

committed by
Greg Kroah-Hartman

parent
c9538018cb
commit
45bd9dd1be
@@ -27,6 +27,9 @@
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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#include <asm/div64.h>
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#if IS_ENABLED(CONFIG_X86_64)
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#include <asm/intel-family.h>
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#endif
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#include <drm/amdgpu_drm.h>
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#include <drm/amdgpu_drm.h>
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#include "ppatomctrl.h"
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#include "ppatomctrl.h"
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#include "atombios.h"
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#include "atombios.h"
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@@ -1606,6 +1609,17 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
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return result;
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return result;
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}
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}
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static bool intel_core_rkl_chk(void)
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{
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#if IS_ENABLED(CONFIG_X86_64)
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struct cpuinfo_x86 *c = &cpu_data(0);
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return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE);
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#else
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return false;
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#endif
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}
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static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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{
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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@@ -1629,7 +1643,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
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data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
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data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
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data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
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data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
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data->pcie_dpm_key_disabled =
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intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
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/* need to set voltage control types before EVV patching */
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/* need to set voltage control types before EVV patching */
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data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
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data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
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data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
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data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
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