Merge tag 'linux-watchdog-5.9-rc1' of git://www.linux-watchdog.org/linux-watchdog
Pull watchdog updates from Wim Van Sebroeck: - f71808e_wdt imporvements - dw_wdt improvements - mlx-wdt: support new watchdog type with longer timeout period - fallthrough pseudo-keyword replacements - overall small fixes and improvements * tag 'linux-watchdog-5.9-rc1' of git://www.linux-watchdog.org/linux-watchdog: (35 commits) watchdog: rti-wdt: balance pm runtime enable calls watchdog: rti-wdt: attach to running watchdog during probe watchdog: add support for adjusting last known HW keepalive time watchdog: use __watchdog_ping in startup watchdog: softdog: Add options 'soft_reboot_cmd' and 'soft_active_on_boot' watchdog: pcwd_usb: remove needless check before usb_free_coherent() watchdog: Replace HTTP links with HTTPS ones dt-bindings: watchdog: renesas,wdt: Document r8a774e1 support watchdog: initialize device before misc_register watchdog: booke_wdt: Add common nowayout parameter driver watchdog: scx200_wdt: Use fallthrough pseudo-keyword watchdog: Use fallthrough pseudo-keyword watchdog: f71808e_wdt: do stricter parameter validation watchdog: f71808e_wdt: clear watchdog timeout occurred flag watchdog: f71808e_wdt: remove use of wrong watchdog_info option watchdog: f71808e_wdt: indicate WDIOF_CARDRESET support in watchdog_info.options docs: watchdog: codify ident.options as superset of possible status flags dt-bindings: watchdog: Add compatible for QCS404, SC7180, SDM845, SM8150 dt-bindings: watchdog: Convert QCOM watchdog timer bindings to YAML watchdog: dw_wdt: Add DebugFS files ...
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@@ -186,7 +186,9 @@
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#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
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#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
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#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
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#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
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#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
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#define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600
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#define MLXPLAT_CPLD_WD_MAX_DEVS 2
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/* mlxplat_priv - platform private data
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@@ -2084,6 +2086,84 @@ static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
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},
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};
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/* Watchdog type3: hardware implementation version 3
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* Can be on all systems. It's differentiated by WD capability bit.
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* Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140)
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* still have only one main watchdog.
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*/
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static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = {
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{
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.label = "action",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
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.bit = 0,
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},
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{
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.label = "timeout",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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.health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
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},
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{
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.label = "timeleft",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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},
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{
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.label = "ping",
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.reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
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.bit = 0,
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},
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{
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.label = "reset",
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.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
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.mask = GENMASK(7, 0) & ~BIT(6),
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.bit = 6,
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},
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};
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static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = {
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{
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.label = "action",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
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.bit = 4,
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},
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{
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.label = "timeout",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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.health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
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},
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{
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.label = "timeleft",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
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.mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
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},
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{
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.label = "ping",
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.reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
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.mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
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.bit = 4,
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},
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};
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static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = {
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{
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.data = mlxplat_mlxcpld_wd_main_regs_type3,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3),
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.version = MLX_WDT_TYPE3,
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.identity = "mlx-wdt-main",
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},
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{
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.data = mlxplat_mlxcpld_wd_aux_regs_type3,
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.counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3),
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.version = MLX_WDT_TYPE3,
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.identity = "mlx-wdt-aux",
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},
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};
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static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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@@ -2114,8 +2194,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
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@@ -2742,6 +2824,27 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
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return 0;
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}
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static int mlxplat_mlxcpld_check_wd_capability(void *regmap)
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{
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u32 regval;
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int i, rc;
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rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
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®val);
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if (rc)
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return rc;
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if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {
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for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) {
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if (mlxplat_wd_data[i])
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mlxplat_wd_data[i] =
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&mlxplat_mlxcpld_wd_set_type3[i];
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}
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}
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return 0;
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}
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static int __init mlxplat_init(void)
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{
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struct mlxplat_priv *priv;
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@@ -2874,6 +2977,9 @@ static int __init mlxplat_init(void)
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}
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/* Add WD drivers. */
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err = mlxplat_mlxcpld_check_wd_capability(priv->regmap);
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if (err)
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goto fail_platform_wd_register;
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for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
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if (mlxplat_wd_data[j]) {
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mlxplat_wd_data[j]->regmap = priv->regmap;
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