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clk: samsung: exynos5433: Add clocks for CMU_G3D domain

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This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
2015-02-02 23:24:06 +09:00
committed by Sylwester Nawrocki
parent 4b8013554b
commit 453e519e5a
2 changed files with 152 additions and 0 deletions
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25
include/dt-bindings/clock/exynos5433.h
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@@ -794,4 +794,29 @@
#define BUSx_NR_CLK 11
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_ACLK_G3D_400 2
#define CLK_MOUT_G3D_PLL 3
#define CLK_DIV_SCLK_HPM_G3D 4
#define CLK_DIV_PCLK_G3D 5
#define CLK_DIV_ACLK_G3D 6
#define CLK_ACLK_BTS_G3D1 7
#define CLK_ACLK_BTS_G3D0 8
#define CLK_ACLK_ASYNCAPBS_G3D 9
#define CLK_ACLK_ASYNCAPBM_G3D 10
#define CLK_ACLK_AHB2APB_G3DP 11
#define CLK_ACLK_G3DNP_150 12
#define CLK_ACLK_G3DND_600 13
#define CLK_ACLK_G3D 14
#define CLK_PCLK_BTS_G3D1 15
#define CLK_PCLK_BTS_G3D0 16
#define CLK_PCLK_PMU_G3D 17
#define CLK_PCLK_SYSREG_G3D 18
#define CLK_SCLK_HPM_G3D 19
#define G3D_NR_CLK 20
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */