staging: mfd: add a PMIC driver for HiSilicon 6421 SPMI version
Add the PMIC SPMI driver for the HiSilicon 6421v600. [mchehab+huawei@kernel.org: keep just the MFD driver on this patch, and renamed filenames to better match other upstream drivers] The compete patch is at: https://github.com/96boards-hikey/linux/commit/08464419fba2 Signed-off-by: Mayulong <mayulong1@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/4ffb2694244baa47387e39e2c5d71243242c1fc1.1597647359.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Mayulong
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
7f3ac6c502
commit
4524ac56cd
165
include/linux/mfd/hi6421-spmi-pmic.h
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165
include/linux/mfd/hi6421-spmi-pmic.h
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/*
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* Header file for device driver Hi6421 PMIC
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*
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* Copyright (c) 2013 Linaro Ltd.
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* Copyright (C) 2011 Hisilicon.
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*
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* Guodong Xu <guodong.xu@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __HISI_PMIC_H
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#define __HISI_PMIC_H
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#include <linux/irqdomain.h>
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#define HISI_REGS_ENA_PROTECT_TIME (0) /* in microseconds */
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#define HISI_ECO_MODE_ENABLE (1)
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#define HISI_ECO_MODE_DISABLE (0)
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typedef int (*pmic_ocp_callback)(char *);
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extern int hisi_pmic_special_ocp_register(char *power_name, pmic_ocp_callback handler);
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struct irq_mask_info {
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int start_addr;
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int array;
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};
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struct irq_info {
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int start_addr;
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int array;
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};
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struct bit_info {
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int addr;
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int bit;
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};
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struct write_lock {
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int addr;
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int val;
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};
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struct hisi_pmic {
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struct resource *res;
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struct device *dev;
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void __iomem *regs;
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spinlock_t lock;
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struct irq_domain *domain;
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int irq;
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int gpio;
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unsigned int *irqs;
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int irqnum;
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int irqarray;
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struct irq_mask_info irq_mask_addr;
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struct irq_info irq_addr;
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int irqnum1;
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int irqarray1;
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struct irq_mask_info irq_mask_addr1;
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struct irq_info irq_addr1;
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struct write_lock normal_lock;
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struct write_lock debug_lock;
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};
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/* 0:disable; 1:enable */
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unsigned int get_uv_mntn_status(void);
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void clear_uv_mntn_resered_reg_bit(void);
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void set_uv_mntn_resered_reg_bit(void);
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#if defined(CONFIG_HISI_PMIC) || defined(CONFIG_HISI_PMIC_PMU_SPMI)
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/* Register Access Helpers */
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u32 hisi_pmic_read(struct hisi_pmic *pmic, int reg);
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void hisi_pmic_write(struct hisi_pmic *pmic, int reg, u32 val);
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void hisi_pmic_rmw(struct hisi_pmic *pmic, int reg, u32 mask, u32 bits);
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unsigned int hisi_pmic_reg_read(int addr);
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void hisi_pmic_reg_write(int addr, int val);
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void hisi_pmic_reg_write_lock(int addr, int val);
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int hisi_pmic_array_read(int addr, char *buff, unsigned int len);
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int hisi_pmic_array_write(int addr, char *buff, unsigned int len);
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extern int hisi_get_pmic_irq_byname(unsigned int pmic_irq_list);
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extern int hisi_pmic_get_vbus_status(void);
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#if defined(CONFIG_HISI_DIEID)
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u32 hisi_pmic_read_sub_pmu(u8 sid ,int reg);
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void hisi_pmic_write_sub_pmu(u8 sid ,int reg, u32 val);
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#endif
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#else
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static inline u32 hisi_pmic_read(struct hisi_pmic *pmic, int reg) { return 0; }
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static inline void hisi_pmic_write(struct hisi_pmic *pmic, int reg, u32 val) {}
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static inline void hisi_pmic_rmw(struct hisi_pmic *pmic, int reg, u32 mask, u32 bits) {}
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static inline unsigned int hisi_pmic_reg_read(int addr) { return 0; }
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static inline void hisi_pmic_reg_write(int addr, int val) {}
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static inline void hisi_pmic_reg_write_lock(int addr, int val) {}
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static inline int hisi_pmic_array_read(int addr, char *buff, unsigned int len) { return 0; }
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static inline int hisi_pmic_array_write(int addr, char *buff, unsigned int len) { return 0; }
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static inline int hisi_get_pmic_irq_byname(unsigned int pmic_irq_list) { return -1; }
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static inline int hisi_pmic_get_vbus_status(void) { return 1; }
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static inline u32 hisi_pmic_read_sub_pmu(u8 sid ,int reg) { return 0; }
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static inline void hisi_pmic_write_sub_pmu(u8 sid ,int reg, u32 val) {}
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#endif
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#ifdef CONFIG_HISI_HI6421V500_PMU
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enum pmic_irq_list {
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POR_D45MR = 0,
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VBUS_CONNECT,
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VBUS_DISCONNECT,
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ALARMON_R,
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HOLD_6S,
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HOLD_1S,
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POWERKEY_UP,
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POWERKEY_DOWN,
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OCP_SCP_R,
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COUL_R,
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VSYS_OV,
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VSYS_UV,
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VSYS_PWROFF_ABS,
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VSYS_PWROFF_DEB,
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THSD_OTMP140,
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THSD_OTMP125,
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HRESETN,
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SIM0_HPD_R = 24,
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SIM0_HPD_F,
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SIM0_HPD_H,
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SIM0_HPD_L,
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SIM1_HPD_R,
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SIM1_HPD_F,
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SIM1_HPD_H,
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SIM1_HPD_L,
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PMIC_IRQ_LIST_MAX,
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};
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#else
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enum pmic_irq_list {
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OTMP = 0,
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VBUS_CONNECT,
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VBUS_DISCONNECT,
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ALARMON_R,
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HOLD_6S,
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HOLD_1S,
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POWERKEY_UP,
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POWERKEY_DOWN,
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OCP_SCP_R,
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COUL_R,
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SIM0_HPD_R,
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SIM0_HPD_F,
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SIM1_HPD_R,
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SIM1_HPD_F,
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PMIC_IRQ_LIST_MAX,
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};
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#endif
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#ifdef CONFIG_HISI_SR_DEBUG
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extern void get_ip_regulator_state(void);
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#endif
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#endif /* __HISI_PMIC_H */
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