Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This merge window brings a good size of cleanups on various platforms.
Among the bigger ones:
- Removal of Samsung s5pc100 and s5p64xx platforms. Both of these
have lacked active support for quite a while, and after asking
around nobody showed interest in keeping them around. If needed,
they could be resurrected in the future but it's more likely that
we would prefer reintroduction of them as DT and
multiplatform-enabled platforms instead.
- OMAP4 controller code register define diet. They defined a lot of
registers that were never actually used, etc.
- Move of some of the Tegra platform code (PMC, APBIO, fuse,
powergate) to drivers/soc so it can be shared with 64-bit code.
This also converts them over to traditional driver models where
possible.
- Removal of legacy gpio-samsung driver, since the last users have
been removed (moved to pinctrl)
Plus a bunch of smaller changes for various platforms that sort of
dissapear in the diffstat for the above. clps711x cleanups, shmobile
header file refactoring/moves for multiplatform friendliness, some
misc cleanups, etc"
* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
drivers: CCI: Correct use of ! and &
video: clcd-versatile: Depend on ARM
video: fix up versatile CLCD helper move
MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
MAINTAINERS: Remove Kirkwood
ARM: tegra: Convert PMC to a driver
soc/tegra: fuse: Set up in early initcall
ARM: tegra: Always lock the CPU reset vector
ARM: tegra: Setup CPU hotplug in a pure initcall
soc/tegra: Implement runtime check for Tegra SoCs
soc/tegra: fuse: fix dummy functions
soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
soc/tegra: Add efuse and apbmisc bindings
soc/tegra: Add efuse driver for Tegra
ARM: tegra: move fuse exports to soc/tegra/fuse.h
ARM: tegra: export apb dma readl/writel
ARM: tegra: Use a function to get the chip ID
ARM: tegra: Sort includes alphabetically
ARM: tegra: Move includes to include/soc/tegra
...
This commit is contained in:
Linus Torvalds
@@ -21,10 +21,7 @@
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#include <asm/div64.h>
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#include "soc.h"
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#include "clock.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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/* DPLL rate rounding: minimum DPLL multiplier, divider values */
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#define DPLL_MIN_MULTIPLIER 2
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@@ -44,20 +41,12 @@
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#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
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(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
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/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
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#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
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#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
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#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
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/*
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* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
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* From device data manual section 4.3 "DPLL and DLL Specifications".
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*/
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
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#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
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#define OMAP3PLUS_DPLL_FINT_MIN 32000
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#define OMAP3PLUS_DPLL_FINT_MAX 52000000
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/* _dpll_test_fint() return codes */
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#define DPLL_FINT_UNDERFLOW -1
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@@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
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/* DPLL divider must result in a valid jitter correction val */
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fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
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if (cpu_is_omap24xx()) {
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/* Should not be called for OMAP2, so warn if it is called */
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WARN(1, "No fint limits available for OMAP2!\n");
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return DPLL_FINT_INVALID;
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} else if (cpu_is_omap3430()) {
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fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
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fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
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} else if (dd->flags & DPLL_J_TYPE) {
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if (dd->flags & DPLL_J_TYPE) {
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fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
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} else {
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fint_min = OMAP3PLUS_DPLL_FINT_MIN;
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fint_max = OMAP3PLUS_DPLL_FINT_MAX;
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fint_min = ti_clk_features.fint_min;
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fint_max = ti_clk_features.fint_max;
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}
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if (fint < fint_min) {
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if (!fint_min || !fint_max) {
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WARN(1, "No fint limits available!\n");
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return DPLL_FINT_INVALID;
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}
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if (fint < ti_clk_features.fint_min) {
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pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
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n);
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dd->max_divider = n;
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ret = DPLL_FINT_UNDERFLOW;
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} else if (fint > fint_max) {
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} else if (fint > ti_clk_features.fint_max) {
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pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
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n);
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dd->min_divider = n;
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ret = DPLL_FINT_INVALID;
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} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
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fint < OMAP3430_DPLL_FINT_BAND2_MIN) {
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} else if (fint > ti_clk_features.fint_band1_max &&
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fint < ti_clk_features.fint_band2_min) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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}
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@@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
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return r;
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}
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/**
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* _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
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* @v: bitfield value of the DPLL enable
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*
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* Checks given DPLL enable bitfield to see whether the DPLL is in bypass
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* mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
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*/
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static int _omap2_dpll_is_in_bypass(u32 v)
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{
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u8 mask, val;
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mask = ti_clk_features.dpll_bypass_vals;
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/*
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* Each set bit in the mask corresponds to a bypass value equal
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* to the bitshift. Go through each set-bit in the mask and
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* compare against the given register value.
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*/
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while (mask) {
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val = __ffs(mask);
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mask ^= (1 << val);
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if (v == val)
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return 1;
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}
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return 0;
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}
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/* Public functions */
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u8 omap2_init_dpll_parent(struct clk_hw *hw)
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{
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@@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
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v >>= __ffs(dd->enable_mask);
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/* Reparent the struct clk in case the dpll is in bypass */
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if (cpu_is_omap24xx()) {
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if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
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v == OMAP2XXX_EN_DPLL_FRBYPASS)
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return 1;
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} else if (cpu_is_omap34xx()) {
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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return 1;
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} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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return 1;
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}
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if (_omap2_dpll_is_in_bypass(v))
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return 1;
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return 0;
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}
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@@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
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v &= dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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if (cpu_is_omap24xx()) {
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if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
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v == OMAP2XXX_EN_DPLL_FRBYPASS)
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return __clk_get_rate(dd->clk_bypass);
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} else if (cpu_is_omap34xx()) {
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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return __clk_get_rate(dd->clk_bypass);
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} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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return __clk_get_rate(dd->clk_bypass);
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}
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if (_omap2_dpll_is_in_bypass(v))
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return __clk_get_rate(dd->clk_bypass);
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v = omap2_clk_readl(clk, dd->mult_div1_reg);
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dpll_mult = v & dd->mult_mask;
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@@ -14,11 +14,11 @@
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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/* Register offsets */
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#define CM_AUTOIDLE 0x30
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#define CM_ICLKEN 0x10
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/* Private functions */
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@@ -46,6 +46,24 @@
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u16 cpu_mask;
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/*
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* Clock features setup. Used instead of CPU type checks.
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*/
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struct ti_clk_features ti_clk_features;
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/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
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#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
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#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
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#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
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/*
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* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
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* From device data manual section 4.3 "DPLL and DLL Specifications".
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*/
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#define OMAP3PLUS_DPLL_FINT_MIN 32000
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#define OMAP3PLUS_DPLL_FINT_MAX 52000000
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/*
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* clkdm_control: if true, then when a clock is enabled in the
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* hardware, its clockdomain will first be enabled; and when a clock
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@@ -287,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
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* 34xx reverses this, just to keep us on our toes
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* AM35xx uses both, depending on the module.
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*/
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if (cpu_is_omap24xx())
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*idlest_val = OMAP24XX_CM_IDLEST_VAL;
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else if (cpu_is_omap34xx())
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*idlest_val = OMAP34XX_CM_IDLEST_VAL;
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else
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BUG();
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*idlest_val = ti_clk_features.cm_idlest_val;
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}
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/**
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@@ -731,3 +743,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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(clk_get_rate(core_ck) / 1000000),
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(clk_get_rate(mpu_ck) / 1000000));
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}
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/**
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* ti_clk_init_features - init clock features struct for the SoC
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*
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* Initializes the clock features struct based on the SoC type.
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*/
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void __init ti_clk_init_features(void)
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{
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/* Fint setup for DPLLs */
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if (cpu_is_omap3430()) {
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ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
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ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
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ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
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ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
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} else {
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ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
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ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
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}
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/* Bypass value setup for DPLLs */
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if (cpu_is_omap24xx()) {
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ti_clk_features.dpll_bypass_vals |=
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(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
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(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
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} else if (cpu_is_omap34xx()) {
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ti_clk_features.dpll_bypass_vals |=
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(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
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(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
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} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
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soc_is_omap54xx() || soc_is_dra7xx()) {
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ti_clk_features.dpll_bypass_vals |=
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(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
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(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
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(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
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}
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/* Jitter correction only available on OMAP343X */
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if (cpu_is_omap343x())
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ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
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/* Idlest value for interface clocks.
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* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
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* 34xx reverses this, just to keep us on our toes
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* AM35xx uses both, depending on the module.
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*/
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if (cpu_is_omap24xx())
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ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
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else if (cpu_is_omap34xx())
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ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
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}
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@@ -101,31 +101,6 @@ struct clockdomain;
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}; \
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DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
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#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
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_parent_ptr, _flags, \
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_clksel_reg, _clksel_mask) \
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static const struct clksel _name##_div[] = { \
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{ \
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.parent = _parent_ptr, \
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.rates = div31_1to31_rates \
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}, \
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{ .parent = NULL }, \
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}; \
|
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static struct clk _name; \
|
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static const char *_name##_parent_names[] = { \
|
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_parent_name, \
|
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}; \
|
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static struct clk_hw_omap _name##_hw = { \
|
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.hw = { \
|
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.clk = &_name, \
|
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}, \
|
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.clksel = _name##_div, \
|
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.clksel_reg = _clksel_reg, \
|
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.clksel_mask = _clksel_mask, \
|
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.ops = &clkhwops_omap4_dpllmx, \
|
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}; \
|
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DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
|
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|
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/* struct clksel_rate.flags possibilities */
|
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#define RATE_IN_242X (1 << 0)
|
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#define RATE_IN_243X (1 << 1)
|
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@@ -248,6 +223,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
|
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|
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extern u16 cpu_mask;
|
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|
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/*
|
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* Clock features setup. Used instead of CPU type checks.
|
||||
*/
|
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struct ti_clk_features {
|
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u32 flags;
|
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long fint_min;
|
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long fint_max;
|
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long fint_band1_max;
|
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long fint_band2_min;
|
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u8 dpll_bypass_vals;
|
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u8 cm_idlest_val;
|
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};
|
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|
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#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
|
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|
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extern struct ti_clk_features ti_clk_features;
|
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|
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extern const struct clkops clkops_omap2_dflt_wait;
|
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extern const struct clkops clkops_dummy;
|
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extern const struct clkops clkops_omap2_dflt;
|
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@@ -286,4 +278,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
|
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extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
|
||||
|
||||
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
|
||||
|
||||
void __init ti_clk_init_features(void);
|
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#endif
|
||||
|
||||
@@ -44,8 +44,7 @@ struct omap3_scratchpad {
|
||||
};
|
||||
|
||||
struct omap3_scratchpad_prcm_block {
|
||||
u32 prm_clksrc_ctrl;
|
||||
u32 prm_clksel;
|
||||
u32 prm_contents[2];
|
||||
u32 cm_contents[11];
|
||||
u32 prcm_block_size;
|
||||
};
|
||||
@@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void)
|
||||
void __iomem *v_addr;
|
||||
u32 offset = 0;
|
||||
v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
|
||||
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
|
||||
OMAP3430_GLOBAL_COLD_RST_MASK) {
|
||||
if (omap3xxx_prm_clear_global_cold_reset()) {
|
||||
for ( ; offset <= max_offset; offset += 0x4)
|
||||
writel_relaxed(0x0, (v_addr + offset));
|
||||
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_RSTST_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void)
|
||||
scratchpad_contents.sdrc_block_offset = 0x64;
|
||||
|
||||
/* Populate the PRCM block contents */
|
||||
prcm_block_contents.prm_clksrc_ctrl =
|
||||
omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
prcm_block_contents.prm_clksel =
|
||||
omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
|
||||
OMAP3_PRM_CLKSEL_OFFSET);
|
||||
|
||||
omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
|
||||
omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
|
||||
|
||||
prcm_block_contents.prcm_block_size = 0x0;
|
||||
@@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void)
|
||||
* Sets the bootmode for IVA2 to idle. This is needed by the PM code to
|
||||
* force disable IVA2 so that it does not prevent any low-power states.
|
||||
*/
|
||||
void omap3_ctrl_set_iva_bootmode_idle(void)
|
||||
static void __init omap3_ctrl_set_iva_bootmode_idle(void)
|
||||
{
|
||||
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
|
||||
OMAP343X_CONTROL_IVA2_BOOTMOD);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
|
||||
*
|
||||
* Sets up the pads controlling the stacked modem in such way that the
|
||||
* device can enter idle.
|
||||
*/
|
||||
static void __init omap3_ctrl_setup_d2d_padconf(void)
|
||||
{
|
||||
u16 mask, padconf;
|
||||
|
||||
/*
|
||||
* In a stand alone OMAP3430 where there is not a stacked
|
||||
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
||||
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
||||
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
|
||||
*/
|
||||
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
||||
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
||||
padconf |= mask;
|
||||
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
||||
|
||||
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
||||
padconf |= mask;
|
||||
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_ctrl_init - does static initializations for control module
|
||||
*
|
||||
* Initializes system control module. This sets up the sysconfig autoidle,
|
||||
* and sets up modem and iva2 so that they can be idled properly.
|
||||
*/
|
||||
void __init omap3_ctrl_init(void)
|
||||
{
|
||||
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
||||
|
||||
omap3_ctrl_set_iva_bootmode_idle();
|
||||
|
||||
omap3_ctrl_setup_d2d_padconf();
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
|
||||
|
||||
@@ -16,11 +16,6 @@
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
|
||||
|
||||
#include "ctrl_module_core_44xx.h"
|
||||
#include "ctrl_module_wkup_44xx.h"
|
||||
#include "ctrl_module_pad_core_44xx.h"
|
||||
#include "ctrl_module_pad_wkup_44xx.h"
|
||||
|
||||
#include "am33xx.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
@@ -254,6 +249,39 @@
|
||||
/* TI81XX CONTROL_DEVCONF register offsets */
|
||||
#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
|
||||
|
||||
/* OMAP4 CONTROL MODULE */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
|
||||
#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
|
||||
#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
|
||||
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
|
||||
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
|
||||
|
||||
/* OMAP4 CONTROL_DSIPHY */
|
||||
#define OMAP4_DSI2_LANEENABLE_SHIFT 29
|
||||
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
|
||||
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
|
||||
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
|
||||
#define OMAP4_DSI1_PIPD_SHIFT 19
|
||||
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
|
||||
#define OMAP4_DSI2_PIPD_SHIFT 14
|
||||
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
|
||||
|
||||
/* OMAP4 CONTROL_CAMERA_RX */
|
||||
#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
|
||||
#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
|
||||
#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
|
||||
#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
|
||||
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
|
||||
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
|
||||
#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
|
||||
#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
|
||||
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
|
||||
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
|
||||
#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
|
||||
#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
|
||||
|
||||
/* OMAP54XX CONTROL STATUS register */
|
||||
#define OMAP5XXX_CONTROL_STATUS 0x134
|
||||
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
|
||||
@@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
|
||||
extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
|
||||
extern void omap3630_ctrl_disable_rta(void);
|
||||
extern int omap3_ctrl_save_padconf(void);
|
||||
extern void omap3_ctrl_set_iva_bootmode_idle(void);
|
||||
void omap3_ctrl_init(void);
|
||||
extern void omap2_set_globals_control(void __iomem *ctrl,
|
||||
void __iomem *ctrl_pad);
|
||||
#else
|
||||
|
||||
@@ -1,392 +0,0 @@
|
||||
/*
|
||||
* OMAP44xx CTRL_MODULE_CORE registers and bitfields
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
*
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Santosh Shilimkar (santosh.shilimkar@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
|
||||
|
||||
|
||||
/* Base address */
|
||||
#define OMAP4_CTRL_MODULE_CORE 0x4a002000
|
||||
|
||||
/* Registers offset */
|
||||
#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
|
||||
#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
|
||||
#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
|
||||
#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
|
||||
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
|
||||
#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
|
||||
#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
|
||||
#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
|
||||
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
|
||||
#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
|
||||
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
|
||||
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
|
||||
#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
|
||||
#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
|
||||
#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
|
||||
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
|
||||
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
|
||||
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
|
||||
|
||||
/* Registers shifts and masks */
|
||||
|
||||
/* IP_REVISION */
|
||||
#define OMAP4_IP_REV_SCHEME_SHIFT 30
|
||||
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
|
||||
#define OMAP4_IP_REV_FUNC_SHIFT 16
|
||||
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
|
||||
#define OMAP4_IP_REV_RTL_SHIFT 11
|
||||
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
|
||||
#define OMAP4_IP_REV_MAJOR_SHIFT 8
|
||||
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
|
||||
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
|
||||
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
|
||||
#define OMAP4_IP_REV_MINOR_SHIFT 0
|
||||
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
|
||||
|
||||
/* IP_HWINFO */
|
||||
#define OMAP4_IP_HWINFO_SHIFT 0
|
||||
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
|
||||
|
||||
/* IP_SYSCONFIG */
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
|
||||
|
||||
/* STD_FUSE_DIE_ID_0 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
|
||||
|
||||
/* ID_CODE */
|
||||
#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_DIE_ID_1 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_DIE_ID_2 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_DIE_ID_3 */
|
||||
#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_PROD_ID_0 */
|
||||
#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_PROD_ID_1 */
|
||||
#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_USB_CONF */
|
||||
#define OMAP4_USB_PROD_ID_SHIFT 16
|
||||
#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
|
||||
#define OMAP4_USB_VENDOR_ID_SHIFT 0
|
||||
#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_VDD_WKUP */
|
||||
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_BGAP */
|
||||
#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_DPLL_0 */
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
|
||||
|
||||
/* STD_FUSE_OPP_DPLL_1 */
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
|
||||
#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
|
||||
|
||||
/* STATUS */
|
||||
#define OMAP4_ATTILA_CONF_SHIFT 11
|
||||
#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
|
||||
#define OMAP4_DEVICE_TYPE_SHIFT 8
|
||||
#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
|
||||
#define OMAP4_SYS_BOOT_SHIFT 0
|
||||
#define OMAP4_SYS_BOOT_MASK (0xff << 0)
|
||||
|
||||
/* DEV_CONF */
|
||||
#define OMAP4_DEV_CONF_SHIFT 1
|
||||
#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
|
||||
#define OMAP4_USBPHY_PD_SHIFT 0
|
||||
#define OMAP4_USBPHY_PD_MASK (1 << 0)
|
||||
|
||||
/* LDOVBB_IVA_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOVBB_MPU_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_IVA_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_MPU_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_CORE_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* TEMP_SENSOR */
|
||||
#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
|
||||
#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
|
||||
#define OMAP4_BGAP_TSHUT_SHIFT 11
|
||||
#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
|
||||
|
||||
/* DPLL_NWELL_TRIM_0 */
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
|
||||
|
||||
/* DPLL_NWELL_TRIM_1 */
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
|
||||
|
||||
/* USBOTGHS_CONTROL */
|
||||
#define OMAP4_DISCHRGVBUS_SHIFT 8
|
||||
#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
|
||||
#define OMAP4_CHRGVBUS_SHIFT 7
|
||||
#define OMAP4_CHRGVBUS_MASK (1 << 7)
|
||||
#define OMAP4_DRVVBUS_SHIFT 6
|
||||
#define OMAP4_DRVVBUS_MASK (1 << 6)
|
||||
#define OMAP4_IDPULLUP_SHIFT 5
|
||||
#define OMAP4_IDPULLUP_MASK (1 << 5)
|
||||
#define OMAP4_IDDIG_SHIFT 4
|
||||
#define OMAP4_IDDIG_MASK (1 << 4)
|
||||
#define OMAP4_SESSEND_SHIFT 3
|
||||
#define OMAP4_SESSEND_MASK (1 << 3)
|
||||
#define OMAP4_VBUSVALID_SHIFT 2
|
||||
#define OMAP4_VBUSVALID_MASK (1 << 2)
|
||||
#define OMAP4_BVALID_SHIFT 1
|
||||
#define OMAP4_BVALID_MASK (1 << 1)
|
||||
#define OMAP4_AVALID_SHIFT 0
|
||||
#define OMAP4_AVALID_MASK (1 << 0)
|
||||
|
||||
/* DSS_CONTROL */
|
||||
#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
|
||||
#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
|
||||
|
||||
/* HWOBS_CONTROL */
|
||||
#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
|
||||
#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
|
||||
#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
|
||||
#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
|
||||
#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
|
||||
#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
|
||||
#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
|
||||
#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
|
||||
|
||||
/* DEBOBS_FINAL_MUX_SEL */
|
||||
#define OMAP4_SELECT_SHIFT 0
|
||||
#define OMAP4_SELECT_MASK (0xffffffff << 0)
|
||||
|
||||
/* DEBOBS_MMR_MPU */
|
||||
#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
|
||||
#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
|
||||
|
||||
/* CONF_SDMA_REQ_SEL0 */
|
||||
#define OMAP4_MULT_SHIFT 0
|
||||
#define OMAP4_MULT_MASK (0x7f << 0)
|
||||
|
||||
/* CONF_CLK_SEL0 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_CLK_SEL1 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_CLK_SEL2 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_FREQLOCK_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_TINITZ_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_PHASELOCK_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DEBUG_SEL_TST_0 */
|
||||
#define OMAP4_MODE_SHIFT 0
|
||||
#define OMAP4_MODE_MASK (0xf << 0)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,236 +0,0 @@
|
||||
/*
|
||||
* OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
*
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Santosh Shilimkar (santosh.shilimkar@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
|
||||
|
||||
|
||||
/* Base address */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
|
||||
|
||||
/* Registers offset */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
|
||||
|
||||
/* Registers shifts and masks */
|
||||
|
||||
/* IP_REVISION */
|
||||
#define OMAP4_IP_REV_SCHEME_SHIFT 30
|
||||
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
|
||||
#define OMAP4_IP_REV_FUNC_SHIFT 16
|
||||
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
|
||||
#define OMAP4_IP_REV_RTL_SHIFT 11
|
||||
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
|
||||
#define OMAP4_IP_REV_MAJOR_SHIFT 8
|
||||
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
|
||||
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
|
||||
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
|
||||
#define OMAP4_IP_REV_MINOR_SHIFT 0
|
||||
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
|
||||
|
||||
/* IP_HWINFO */
|
||||
#define OMAP4_IP_HWINFO_SHIFT 0
|
||||
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
|
||||
|
||||
/* IP_SYSCONFIG */
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
|
||||
|
||||
/* PADCONF_WAKEUPEVENT_0 */
|
||||
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
|
||||
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
|
||||
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
|
||||
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
|
||||
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
|
||||
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
|
||||
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
|
||||
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
|
||||
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
|
||||
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
|
||||
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
|
||||
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
|
||||
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
|
||||
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
|
||||
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
|
||||
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
|
||||
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
|
||||
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
|
||||
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
|
||||
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
|
||||
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
|
||||
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
|
||||
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
|
||||
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
|
||||
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
|
||||
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
|
||||
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
|
||||
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
|
||||
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
|
||||
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
|
||||
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
|
||||
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
|
||||
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
|
||||
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
|
||||
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
|
||||
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
|
||||
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
|
||||
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
|
||||
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
|
||||
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
|
||||
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
|
||||
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
|
||||
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
|
||||
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
|
||||
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
|
||||
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
|
||||
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
|
||||
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
|
||||
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
|
||||
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
|
||||
|
||||
/* CONTROL_SMART1NOPMIO_PADCONF_0 */
|
||||
#define OMAP4_FREF_DR0_SC_SHIFT 30
|
||||
#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
|
||||
#define OMAP4_FREF_DR1_SC_SHIFT 28
|
||||
#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
|
||||
#define OMAP4_FREF_DR4_SC_SHIFT 26
|
||||
#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
|
||||
#define OMAP4_FREF_DR5_SC_SHIFT 24
|
||||
#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
|
||||
#define OMAP4_FREF_DR6_SC_SHIFT 22
|
||||
#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
|
||||
#define OMAP4_FREF_DR7_SC_SHIFT 20
|
||||
#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
|
||||
#define OMAP4_GPIO_DR7_SC_SHIFT 18
|
||||
#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
|
||||
#define OMAP4_DPM_DR0_SC_SHIFT 14
|
||||
#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
|
||||
#define OMAP4_SIM_DR0_SC_SHIFT 12
|
||||
#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
|
||||
|
||||
/* CONTROL_SMART1NOPMIO_PADCONF_1 */
|
||||
#define OMAP4_FREF_DR0_LB_SHIFT 30
|
||||
#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
|
||||
#define OMAP4_FREF_DR1_LB_SHIFT 28
|
||||
#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
|
||||
#define OMAP4_FREF_DR4_LB_SHIFT 26
|
||||
#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
|
||||
#define OMAP4_FREF_DR5_LB_SHIFT 24
|
||||
#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
|
||||
#define OMAP4_FREF_DR6_LB_SHIFT 22
|
||||
#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
|
||||
#define OMAP4_FREF_DR7_LB_SHIFT 20
|
||||
#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
|
||||
#define OMAP4_GPIO_DR7_LB_SHIFT 18
|
||||
#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
|
||||
#define OMAP4_DPM_DR0_LB_SHIFT 14
|
||||
#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
|
||||
#define OMAP4_SIM_DR0_LB_SHIFT 12
|
||||
#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
|
||||
|
||||
/* CONTROL_PADCONF_MODE */
|
||||
#define OMAP4_VDDS_DV_FREF_SHIFT 31
|
||||
#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
|
||||
#define OMAP4_VDDS_DV_BANK2_SHIFT 30
|
||||
#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
|
||||
|
||||
/* CONTROL_XTAL_OSCILLATOR */
|
||||
#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
|
||||
#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
|
||||
#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
|
||||
#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
|
||||
|
||||
/* CONTROL_USIMIO */
|
||||
#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
|
||||
#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
|
||||
#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
|
||||
#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
|
||||
#define OMAP4_USIM_PWRDNZ_SHIFT 28
|
||||
#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
|
||||
|
||||
/* CONTROL_I2C_2 */
|
||||
#define OMAP4_SR_SDA_GLFENB_SHIFT 31
|
||||
#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
|
||||
#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
|
||||
#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
|
||||
#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
|
||||
#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
|
||||
#define OMAP4_SR_SCL_GLFENB_SHIFT 27
|
||||
#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
|
||||
#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
|
||||
#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
|
||||
#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
|
||||
#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
|
||||
|
||||
/* CONTROL_JTAG */
|
||||
#define OMAP4_JTAG_NTRST_EN_SHIFT 31
|
||||
#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
|
||||
#define OMAP4_JTAG_TCK_EN_SHIFT 30
|
||||
#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
|
||||
#define OMAP4_JTAG_RTCK_EN_SHIFT 29
|
||||
#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
|
||||
#define OMAP4_JTAG_TDI_EN_SHIFT 28
|
||||
#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
|
||||
#define OMAP4_JTAG_TDO_EN_SHIFT 27
|
||||
#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
|
||||
|
||||
/* CONTROL_SYS */
|
||||
#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
|
||||
#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_RW */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_R */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_R_C0 */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
|
||||
|
||||
#endif
|
||||
@@ -28,11 +28,8 @@
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "clockdomain.h"
|
||||
#include "clock.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
|
||||
#define DPLL_AUTOIDLE_DISABLE 0x0
|
||||
@@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
|
||||
* Set jitter correction. Jitter correction applicable for OMAP343X
|
||||
* only since freqsel field is no longer present on other devices.
|
||||
*/
|
||||
if (cpu_is_omap343x()) {
|
||||
if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
|
||||
v = omap2_clk_readl(clk, dd->control_reg);
|
||||
v &= ~dd->freqsel_mask;
|
||||
v |= freqsel << __ffs(dd->freqsel_mask);
|
||||
@@ -512,7 +509,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return -EINVAL;
|
||||
|
||||
/* Freqsel is available only on OMAP343X devices */
|
||||
if (cpu_is_omap343x()) {
|
||||
if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
|
||||
freqsel = _omap3_dpll_compute_freqsel(clk,
|
||||
dd->last_rounded_n);
|
||||
WARN_ON(!freqsel);
|
||||
|
||||
@@ -15,10 +15,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "clock.h"
|
||||
#include "clock44xx.h"
|
||||
#include "cm-regbits-44xx.h"
|
||||
|
||||
/*
|
||||
* Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
|
||||
@@ -29,13 +26,23 @@
|
||||
#define OMAP4_DPLL_LP_FINT_MAX 1000000
|
||||
#define OMAP4_DPLL_LP_FOUT_MAX 100000000
|
||||
|
||||
/*
|
||||
* Bitfield declarations
|
||||
*/
|
||||
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
|
||||
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
|
||||
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
|
||||
|
||||
/* Static rate multiplier for OMAP4 REGM4XEN clocks */
|
||||
#define OMAP4430_REGM4XEN_MULT 4
|
||||
|
||||
/* Supported only on OMAP4 */
|
||||
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
|
||||
{
|
||||
u32 v;
|
||||
u32 mask;
|
||||
|
||||
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
|
||||
if (!clk || !clk->clksel_reg)
|
||||
return -EINVAL;
|
||||
|
||||
mask = clk->flags & CLOCK_CLKOUTX2 ?
|
||||
@@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
|
||||
u32 v;
|
||||
u32 mask;
|
||||
|
||||
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
|
||||
if (!clk || !clk->clksel_reg)
|
||||
return;
|
||||
|
||||
mask = clk->flags & CLOCK_CLKOUTX2 ?
|
||||
@@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
|
||||
u32 v;
|
||||
u32 mask;
|
||||
|
||||
if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
|
||||
if (!clk || !clk->clksel_reg)
|
||||
return;
|
||||
|
||||
mask = clk->flags & CLOCK_CLKOUTX2 ?
|
||||
|
||||
@@ -24,25 +24,6 @@
|
||||
/* minimum size for IO mapping */
|
||||
#define NAND_IO_SIZE 4
|
||||
|
||||
static struct resource gpmc_nand_resource[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device gpmc_nand_device = {
|
||||
.name = "omap2-nand",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(gpmc_nand_resource),
|
||||
.resource = gpmc_nand_resource,
|
||||
};
|
||||
|
||||
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
|
||||
{
|
||||
/* platforms which support all ECC schemes */
|
||||
@@ -95,43 +76,41 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
||||
{
|
||||
int err = 0;
|
||||
struct gpmc_settings s;
|
||||
struct device *dev = &gpmc_nand_device.dev;
|
||||
struct platform_device *pdev;
|
||||
struct resource gpmc_nand_res[] = {
|
||||
{ .flags = IORESOURCE_MEM, },
|
||||
{ .flags = IORESOURCE_IRQ, },
|
||||
{ .flags = IORESOURCE_IRQ, },
|
||||
};
|
||||
|
||||
memset(&s, 0, sizeof(struct gpmc_settings));
|
||||
|
||||
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
|
||||
BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
|
||||
|
||||
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
|
||||
(unsigned long *)&gpmc_nand_resource[0].start);
|
||||
(unsigned long *)&gpmc_nand_res[0].start);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
|
||||
gpmc_nand_data->cs, err);
|
||||
pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
|
||||
gpmc_nand_data->cs, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
|
||||
NAND_IO_SIZE - 1;
|
||||
|
||||
gpmc_nand_resource[1].start =
|
||||
gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
|
||||
gpmc_nand_resource[2].start =
|
||||
gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
|
||||
gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
|
||||
gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
|
||||
gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
|
||||
|
||||
if (gpmc_t) {
|
||||
err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
|
||||
pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
memset(&s, 0, sizeof(struct gpmc_settings));
|
||||
if (gpmc_nand_data->of_node)
|
||||
gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
|
||||
else
|
||||
gpmc_set_legacy(gpmc_nand_data, &s);
|
||||
|
||||
s.device_nand = true;
|
||||
|
||||
err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
@@ -143,18 +122,34 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
||||
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
|
||||
|
||||
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
|
||||
dev_err(dev, "Unsupported NAND ECC scheme selected\n");
|
||||
return -EINVAL;
|
||||
pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
|
||||
err = -EINVAL;
|
||||
goto out_free_cs;
|
||||
}
|
||||
|
||||
err = platform_device_register(&gpmc_nand_device);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "Unable to register NAND device\n");
|
||||
goto out_free_cs;
|
||||
|
||||
pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs);
|
||||
if (pdev) {
|
||||
err = platform_device_add_resources(pdev, gpmc_nand_res,
|
||||
ARRAY_SIZE(gpmc_nand_res));
|
||||
if (!err)
|
||||
pdev->dev.platform_data = gpmc_nand_data;
|
||||
} else {
|
||||
err = -ENOMEM;
|
||||
}
|
||||
if (err)
|
||||
goto out_free_pdev;
|
||||
|
||||
err = platform_device_add(pdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Unable to register NAND device\n");
|
||||
goto out_free_pdev;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_pdev:
|
||||
platform_device_put(pdev);
|
||||
out_free_cs:
|
||||
gpmc_cs_free(gpmc_nand_data->cs);
|
||||
|
||||
|
||||
@@ -728,6 +728,8 @@ int __init omap_clk_init(void)
|
||||
if (!omap_clk_soc_init)
|
||||
return 0;
|
||||
|
||||
ti_clk_init_features();
|
||||
|
||||
ret = of_prcm_init();
|
||||
if (!ret)
|
||||
ret = omap_clk_soc_init();
|
||||
|
||||
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
|
||||
|
||||
/* Clear old wake-up events */
|
||||
/* REVISIT: These write to reserved bits? */
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
|
||||
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
|
||||
omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
|
||||
omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
|
||||
omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
|
||||
|
||||
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
|
||||
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
|
||||
@@ -104,23 +104,18 @@ no_sleep:
|
||||
clk_enable(osc_ck);
|
||||
|
||||
/* clear CORE wake-up events */
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
|
||||
omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
|
||||
omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
|
||||
|
||||
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
|
||||
omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
|
||||
omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
|
||||
|
||||
/* MPU domain wake events */
|
||||
l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
|
||||
if (l & 0x01)
|
||||
omap2_prm_write_mod_reg(0x01, OCP_MOD,
|
||||
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
|
||||
if (l & 0x20)
|
||||
omap2_prm_write_mod_reg(0x20, OCP_MOD,
|
||||
OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
|
||||
omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
|
||||
0x1);
|
||||
|
||||
/* Mask future PRCM-to-MPU interrupts */
|
||||
omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
|
||||
omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
|
||||
0x20);
|
||||
|
||||
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
|
||||
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
|
||||
@@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void)
|
||||
* it is in retention mode. */
|
||||
if (omap2_allow_mpu_retention()) {
|
||||
/* REVISIT: These write to reserved bits? */
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
|
||||
omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
|
||||
omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
|
||||
omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
|
||||
omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
|
||||
|
||||
/* Try to enter MPU retention */
|
||||
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
|
||||
|
||||
@@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* PRCM Interrupt Handler Helper Function
|
||||
*
|
||||
* The purpose of this function is to clear any wake-up events latched
|
||||
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
|
||||
* may occur whilst attempting to clear a PM_WKST_x register and thus
|
||||
* set another bit in this register. A while loop is used to ensure
|
||||
* that any peripheral wake-up events occurring while attempting to
|
||||
* clear the PM_WKST_x are detected and cleared.
|
||||
*/
|
||||
static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
|
||||
{
|
||||
u32 wkst, fclk, iclk, clken;
|
||||
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
|
||||
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
|
||||
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
|
||||
u16 grpsel_off = (regs == 3) ?
|
||||
OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
|
||||
int c = 0;
|
||||
|
||||
wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
||||
wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
|
||||
wkst &= ~ignore_bits;
|
||||
if (wkst) {
|
||||
iclk = omap2_cm_read_mod_reg(module, iclk_off);
|
||||
fclk = omap2_cm_read_mod_reg(module, fclk_off);
|
||||
while (wkst) {
|
||||
clken = wkst;
|
||||
omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
|
||||
/*
|
||||
* For USBHOST, we don't know whether HOST1 or
|
||||
* HOST2 woke us up, so enable both f-clocks
|
||||
*/
|
||||
if (module == OMAP3430ES2_USBHOST_MOD)
|
||||
clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
|
||||
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
|
||||
omap2_prm_write_mod_reg(wkst, module, wkst_off);
|
||||
wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
||||
wkst &= ~ignore_bits;
|
||||
c++;
|
||||
}
|
||||
omap2_cm_write_mod_reg(iclk, module, iclk_off);
|
||||
omap2_cm_write_mod_reg(fclk, module, fclk_off);
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
|
||||
{
|
||||
int c;
|
||||
|
||||
c = prcm_clear_mod_irqs(WKUP_MOD, 1,
|
||||
~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
|
||||
c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
|
||||
~(OMAP3430_ST_IO_MASK |
|
||||
OMAP3430_ST_IO_CHAIN_MASK));
|
||||
|
||||
return c ? IRQ_HANDLED : IRQ_NONE;
|
||||
}
|
||||
@@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
|
||||
* these are handled in a separate handler to avoid acking
|
||||
* IO events before parsing in mux code
|
||||
*/
|
||||
c = prcm_clear_mod_irqs(WKUP_MOD, 1,
|
||||
OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
|
||||
c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
|
||||
c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
|
||||
c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
|
||||
OMAP3430_ST_IO_MASK |
|
||||
OMAP3430_ST_IO_CHAIN_MASK);
|
||||
c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
|
||||
c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
|
||||
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
||||
c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
|
||||
c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
|
||||
c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
|
||||
c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
|
||||
}
|
||||
|
||||
return c ? IRQ_HANDLED : IRQ_NONE;
|
||||
@@ -399,159 +353,11 @@ restore:
|
||||
#define omap3_pm_suspend NULL
|
||||
#endif /* CONFIG_SUSPEND */
|
||||
|
||||
|
||||
/**
|
||||
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
|
||||
* retention
|
||||
*
|
||||
* In cases where IVA2 is activated by bootcode, it may prevent
|
||||
* full-chip retention or off-mode because it is not idle. This
|
||||
* function forces the IVA2 into idle state so it can go
|
||||
* into retention/off and thus allow full-chip retention/off.
|
||||
*
|
||||
**/
|
||||
static void __init omap3_iva_idle(void)
|
||||
{
|
||||
/* ensure IVA2 clock is disabled */
|
||||
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* if no clock activity, nothing else to do */
|
||||
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
||||
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
||||
return;
|
||||
|
||||
/* Reset IVA2 */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
||||
OMAP3430_RST2_IVA2_MASK |
|
||||
OMAP3430_RST3_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
|
||||
/* Enable IVA2 clock */
|
||||
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* Set IVA2 boot mode to 'idle' */
|
||||
omap3_ctrl_set_iva_bootmode_idle();
|
||||
|
||||
/* Un-reset IVA2 */
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
|
||||
/* Disable IVA2 clock */
|
||||
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* Reset IVA2 */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
||||
OMAP3430_RST2_IVA2_MASK |
|
||||
OMAP3430_RST3_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
static void __init omap3_d2d_idle(void)
|
||||
{
|
||||
u16 mask, padconf;
|
||||
|
||||
/* In a stand alone OMAP3430 where there is not a stacked
|
||||
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
||||
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
||||
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
||||
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
||||
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
||||
padconf |= mask;
|
||||
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
||||
|
||||
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
||||
padconf |= mask;
|
||||
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
||||
|
||||
/* reset modem */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
||||
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
||||
CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
static void __init prcm_setup_regs(void)
|
||||
{
|
||||
u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
|
||||
OMAP3630_EN_UART4_MASK : 0;
|
||||
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
|
||||
OMAP3630_GRPSEL_UART4_MASK : 0;
|
||||
omap3_ctrl_init();
|
||||
|
||||
/* XXX This should be handled by hwmod code or SCM init code */
|
||||
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
||||
|
||||
/*
|
||||
* Enable control of expternal oscillator through
|
||||
* sys_clkreq. In the long run clock framework should
|
||||
* take care of this.
|
||||
*/
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
||||
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
|
||||
/* setup wakup source */
|
||||
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
||||
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
||||
WKUP_MOD, PM_WKEN);
|
||||
/* No need to write EN_IO, that is always enabled */
|
||||
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
||||
OMAP3430_GRPSEL_GPT1_MASK |
|
||||
OMAP3430_GRPSEL_GPT12_MASK,
|
||||
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Enable PM_WKEN to support DSS LPR */
|
||||
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
||||
OMAP3430_DSS_MOD, PM_WKEN);
|
||||
|
||||
/* Enable wakeups in PER */
|
||||
omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
|
||||
OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
|
||||
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
|
||||
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
|
||||
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
|
||||
OMAP3430_EN_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, PM_WKEN);
|
||||
/* and allow them to wake up MPU */
|
||||
omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
|
||||
OMAP3430_GRPSEL_GPIO2_MASK |
|
||||
OMAP3430_GRPSEL_GPIO3_MASK |
|
||||
OMAP3430_GRPSEL_GPIO4_MASK |
|
||||
OMAP3430_GRPSEL_GPIO5_MASK |
|
||||
OMAP3430_GRPSEL_GPIO6_MASK |
|
||||
OMAP3430_GRPSEL_UART3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP2_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Don't attach IVA interrupts */
|
||||
if (omap3_has_iva()) {
|
||||
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL);
|
||||
}
|
||||
|
||||
/* Clear any pending 'reset' flags */
|
||||
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
|
||||
|
||||
/* Clear any pending PRCM interrupts */
|
||||
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
|
||||
/*
|
||||
* We need to idle iva2_pwrdm even on am3703 with no iva2.
|
||||
*/
|
||||
omap3_iva_idle();
|
||||
|
||||
omap3_d2d_idle();
|
||||
omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
|
||||
}
|
||||
|
||||
void omap3_pm_off_mode_enable(int enable)
|
||||
|
||||
@@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void)
|
||||
omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
|
||||
* @module: PRM module to clear wakeups from
|
||||
* @regs: register offset to clear
|
||||
* @wkst_mask: wakeup status mask to clear
|
||||
*
|
||||
* Clears wakeup status bits for a given module, so that the device can
|
||||
* re-enter idle.
|
||||
*/
|
||||
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
|
||||
{
|
||||
u32 wkst;
|
||||
|
||||
wkst = omap2_prm_read_mod_reg(module, regs);
|
||||
wkst &= wkst_mask;
|
||||
omap2_prm_write_mod_reg(wkst, module, regs);
|
||||
}
|
||||
|
||||
int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
|
||||
{
|
||||
omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
|
||||
|
||||
@@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
|
||||
extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
|
||||
|
||||
extern void omap2xxx_prm_dpll_reset(void);
|
||||
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
|
||||
|
||||
extern int __init omap2xxx_prm_init(void);
|
||||
|
||||
|
||||
@@ -26,6 +26,8 @@
|
||||
#include "prm2xxx_3xxx.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
#include "cm3xxx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
static const struct omap_prcm_irq omap3_prcm_irqs[] = {
|
||||
OMAP_PRCM_IRQ("wkup", 0, 0),
|
||||
@@ -205,6 +207,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
|
||||
OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
|
||||
* @module: PRM module to clear wakeups from
|
||||
* @regs: register set to clear, 1 or 3
|
||||
* @ignore_bits: wakeup status bits to ignore
|
||||
*
|
||||
* The purpose of this function is to clear any wake-up events latched
|
||||
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
|
||||
* may occur whilst attempting to clear a PM_WKST_x register and thus
|
||||
* set another bit in this register. A while loop is used to ensure
|
||||
* that any peripheral wake-up events occurring while attempting to
|
||||
* clear the PM_WKST_x are detected and cleared.
|
||||
*/
|
||||
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
|
||||
{
|
||||
u32 wkst, fclk, iclk, clken;
|
||||
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
|
||||
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
|
||||
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
|
||||
u16 grpsel_off = (regs == 3) ?
|
||||
OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
|
||||
int c = 0;
|
||||
|
||||
wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
||||
wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
|
||||
wkst &= ~ignore_bits;
|
||||
if (wkst) {
|
||||
iclk = omap2_cm_read_mod_reg(module, iclk_off);
|
||||
fclk = omap2_cm_read_mod_reg(module, fclk_off);
|
||||
while (wkst) {
|
||||
clken = wkst;
|
||||
omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
|
||||
/*
|
||||
* For USBHOST, we don't know whether HOST1 or
|
||||
* HOST2 woke us up, so enable both f-clocks
|
||||
*/
|
||||
if (module == OMAP3430ES2_USBHOST_MOD)
|
||||
clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
|
||||
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
|
||||
omap2_prm_write_mod_reg(wkst, module, wkst_off);
|
||||
wkst = omap2_prm_read_mod_reg(module, wkst_off);
|
||||
wkst &= ~ignore_bits;
|
||||
c++;
|
||||
}
|
||||
omap2_cm_write_mod_reg(iclk, module, iclk_off);
|
||||
omap2_cm_write_mod_reg(fclk, module, fclk_off);
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_prm_reset_modem - toggle reset signal for modem
|
||||
*
|
||||
* Toggles the reset signal to modem IP block. Required to allow
|
||||
* OMAP3430 without stacked modem to idle properly.
|
||||
*/
|
||||
void __init omap3_prm_reset_modem(void)
|
||||
{
|
||||
omap2_prm_write_mod_reg(
|
||||
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
||||
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
||||
CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_prm_init_pm - initialize PM related registers for PRM
|
||||
* @has_uart4: SoC has UART4
|
||||
* @has_iva: SoC has IVA
|
||||
*
|
||||
* Initializes PRM registers for PM use. Called from PM init.
|
||||
*/
|
||||
void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
|
||||
{
|
||||
u32 en_uart4_mask;
|
||||
u32 grpsel_uart4_mask;
|
||||
|
||||
/*
|
||||
* Enable control of expternal oscillator through
|
||||
* sys_clkreq. In the long run clock framework should
|
||||
* take care of this.
|
||||
*/
|
||||
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
||||
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
|
||||
/* setup wakup source */
|
||||
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
||||
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
||||
WKUP_MOD, PM_WKEN);
|
||||
/* No need to write EN_IO, that is always enabled */
|
||||
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
||||
OMAP3430_GRPSEL_GPT1_MASK |
|
||||
OMAP3430_GRPSEL_GPT12_MASK,
|
||||
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Enable PM_WKEN to support DSS LPR */
|
||||
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
||||
OMAP3430_DSS_MOD, PM_WKEN);
|
||||
|
||||
if (has_uart4) {
|
||||
en_uart4_mask = OMAP3630_EN_UART4_MASK;
|
||||
grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
|
||||
}
|
||||
|
||||
/* Enable wakeups in PER */
|
||||
omap2_prm_write_mod_reg(en_uart4_mask |
|
||||
OMAP3430_EN_GPIO2_MASK |
|
||||
OMAP3430_EN_GPIO3_MASK |
|
||||
OMAP3430_EN_GPIO4_MASK |
|
||||
OMAP3430_EN_GPIO5_MASK |
|
||||
OMAP3430_EN_GPIO6_MASK |
|
||||
OMAP3430_EN_UART3_MASK |
|
||||
OMAP3430_EN_MCBSP2_MASK |
|
||||
OMAP3430_EN_MCBSP3_MASK |
|
||||
OMAP3430_EN_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, PM_WKEN);
|
||||
|
||||
/* and allow them to wake up MPU */
|
||||
omap2_prm_write_mod_reg(grpsel_uart4_mask |
|
||||
OMAP3430_GRPSEL_GPIO2_MASK |
|
||||
OMAP3430_GRPSEL_GPIO3_MASK |
|
||||
OMAP3430_GRPSEL_GPIO4_MASK |
|
||||
OMAP3430_GRPSEL_GPIO5_MASK |
|
||||
OMAP3430_GRPSEL_GPIO6_MASK |
|
||||
OMAP3430_GRPSEL_UART3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP2_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP3_MASK |
|
||||
OMAP3430_GRPSEL_MCBSP4_MASK,
|
||||
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
||||
|
||||
/* Don't attach IVA interrupts */
|
||||
if (has_iva) {
|
||||
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
||||
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
|
||||
OMAP3430_PM_IVAGRPSEL);
|
||||
}
|
||||
|
||||
/* Clear any pending 'reset' flags */
|
||||
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
||||
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
|
||||
OMAP2_RM_RSTST);
|
||||
|
||||
/* Clear any pending PRCM interrupts */
|
||||
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
|
||||
/* We need to idle iva2_pwrdm even on am3703 with no iva2. */
|
||||
omap3xxx_prm_iva_idle();
|
||||
|
||||
omap3_prm_reset_modem();
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
|
||||
*
|
||||
@@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void)
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention
|
||||
*
|
||||
* In cases where IVA2 is activated by bootcode, it may prevent
|
||||
* full-chip retention or off-mode because it is not idle. This
|
||||
* function forces the IVA2 into idle state so it can go
|
||||
* into retention/off and thus allow full-chip retention/off.
|
||||
*/
|
||||
void omap3xxx_prm_iva_idle(void)
|
||||
{
|
||||
/* ensure IVA2 clock is disabled */
|
||||
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* if no clock activity, nothing else to do */
|
||||
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
||||
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
||||
return;
|
||||
|
||||
/* Reset IVA2 */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
||||
OMAP3430_RST2_IVA2_MASK |
|
||||
OMAP3430_RST3_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
|
||||
/* Enable IVA2 clock */
|
||||
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* Un-reset IVA2 */
|
||||
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
|
||||
/* Disable IVA2 clock */
|
||||
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
||||
|
||||
/* Reset IVA2 */
|
||||
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
||||
OMAP3430_RST2_IVA2_MASK |
|
||||
OMAP3430_RST3_IVA2_MASK,
|
||||
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status
|
||||
* and clears it if asserted
|
||||
*
|
||||
* Checks if cold-reset has occurred and clears the status bit if yes. Returns
|
||||
* 1 if cold-reset has occurred, 0 otherwise.
|
||||
*/
|
||||
int omap3xxx_prm_clear_global_cold_reset(void)
|
||||
{
|
||||
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
|
||||
OMAP3430_GLOBAL_COLD_RST_MASK) {
|
||||
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_RSTST_OFFSET);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void omap3_prm_save_scratchpad_contents(u32 *ptr)
|
||||
{
|
||||
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
||||
|
||||
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_CLKSEL_OFFSET);
|
||||
}
|
||||
|
||||
/* Powerdomain low-level functions */
|
||||
|
||||
static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
||||
|
||||
@@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void);
|
||||
|
||||
extern int __init omap3xxx_prm_init(void);
|
||||
extern u32 omap3xxx_prm_get_reset_sources(void);
|
||||
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
|
||||
void omap3xxx_prm_iva_idle(void);
|
||||
void omap3_prm_reset_modem(void);
|
||||
int omap3xxx_prm_clear_global_cold_reset(void);
|
||||
void omap3_prm_save_scratchpad_contents(u32 *ptr);
|
||||
void omap3_prm_init_pm(bool has_uart4, bool has_iva);
|
||||
|
||||
#endif /* __ASSEMBLER */
|
||||
|
||||
|
||||
@@ -95,7 +95,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
|
||||
dev_t.t_avdp_w = t_scsnh_advnh;
|
||||
dev_t.cyc_aavdh_we = 3;
|
||||
dev_t.cyc_wpl = 6;
|
||||
dev_t.t_ce_rdyz = 7000;
|
||||
|
||||
gpmc_calc_timings(&t, &tusb_sync, &dev_t);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user