perf_counter: powerpc: Use unsigned long for register and constraint values
This changes the powerpc perf_counter back-end to use unsigned long types for hardware register values and for the value/mask pairs used in checking whether a given set of events fit within the hardware constraints. This is in preparation for adding support for the PMU on some 32-bit powerpc processors. On 32-bit processors the hardware registers are only 32 bits wide, and the PMU structure is generally simpler, so 32 bits should be ample for expressing the hardware constraints. On 64-bit processors, unsigned long is 64 bits wide, so using unsigned long vs. u64 (unsigned long long) makes no actual difference. This makes some other very minor changes: adjusting whitespace to line things up in initialized structures, and simplifying some code in hw_perf_disable(). Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: linuxppc-dev@ozlabs.org Cc: benh@kernel.crashing.org LKML-Reference: <19000.55473.26174.331511@cargo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paul Mackerras
committed by
Ingo Molnar
Ingo Molnar
parent
105988c015
commit
448d64f8f4
@@ -130,20 +130,21 @@ static const int grsel_shift[8] = {
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};
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/* Masks and values for using events from the various units */
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static u64 unit_cons[PM_LASTUNIT+1][2] = {
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[PM_FPU] = { 0xc0002000000000ull, 0x00001000000000ull },
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[PM_ISU0] = { 0x00002000000000ull, 0x00000800000000ull },
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[PM_ISU1] = { 0xc0002000000000ull, 0xc0001000000000ull },
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[PM_IFU] = { 0xc0002000000000ull, 0x80001000000000ull },
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[PM_IDU] = { 0x30002000000000ull, 0x00000400000000ull },
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[PM_GRS] = { 0x30002000000000ull, 0x30000400000000ull },
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static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
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[PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul },
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[PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul },
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[PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul },
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[PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul },
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[PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul },
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[PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul },
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};
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static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
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static int power5_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp)
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{
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int pmc, byte, unit, sh;
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int bit, fmask;
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u64 mask = 0, value = 0;
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unsigned long mask = 0, value = 0;
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int grp = -1;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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@@ -178,8 +179,9 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
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bit = event & 7;
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fmask = (bit == 6)? 7: 3;
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sh = grsel_shift[bit];
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mask |= (u64)fmask << sh;
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value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
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mask |= (unsigned long)fmask << sh;
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value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
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<< sh;
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}
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/*
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* Bus events on bytes 0 and 2 can be counted
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@@ -188,22 +190,22 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
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if (!pmc)
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grp = byte & 1;
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/* Set byte lane select field */
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mask |= 0xfULL << (24 - 4 * byte);
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value |= (u64)unit << (24 - 4 * byte);
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mask |= 0xfUL << (24 - 4 * byte);
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value |= (unsigned long)unit << (24 - 4 * byte);
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}
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if (grp == 0) {
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/* increment PMC1/2 field */
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mask |= 0x200000000ull;
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value |= 0x080000000ull;
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mask |= 0x200000000ul;
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value |= 0x080000000ul;
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} else if (grp == 1) {
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/* increment PMC3/4 field */
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mask |= 0x40000000ull;
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value |= 0x10000000ull;
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mask |= 0x40000000ul;
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value |= 0x10000000ul;
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}
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if (pmc < 5) {
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/* need a counter from PMC1-4 set */
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mask |= 0x8000000000000ull;
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value |= 0x1000000000000ull;
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mask |= 0x8000000000000ul;
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value |= 0x1000000000000ul;
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}
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*maskp = mask;
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*valp = value;
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@@ -383,10 +385,10 @@ static int power5_marked_instr_event(u64 event)
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}
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static int power5_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], u64 mmcr[])
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unsigned int hwc[], unsigned long mmcr[])
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{
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u64 mmcr1 = 0;
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u64 mmcra = 0;
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unsigned long mmcr1 = 0;
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unsigned long mmcra = 0;
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unsigned int pmc, unit, byte, psel;
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unsigned int ttm, grp;
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int i, isbus, bit, grsel;
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@@ -457,7 +459,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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continue;
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if (ttmuse++)
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return -1;
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mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
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mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
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}
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ttmuse = 0;
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for (; i <= PM_GRS; ++i) {
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@@ -465,7 +467,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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continue;
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if (ttmuse++)
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return -1;
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mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
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mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
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}
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if (ttmuse > 1)
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return -1;
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@@ -480,10 +482,11 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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unit = PM_ISU0_ALT;
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} else if (unit == PM_LSU1 + 1) {
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/* select lower word of LSU1 for this byte */
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mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
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mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
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}
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ttm = unit >> 2;
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mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
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mmcr1 |= (unsigned long)ttm
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<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
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}
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/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
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@@ -513,7 +516,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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--pmc;
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if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
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/* add events on higher-numbered bus */
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mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
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mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
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} else {
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/* Instructions or run cycles on PMC5/6 */
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--pmc;
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@@ -521,7 +524,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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if (isbus && unit == PM_GRS) {
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bit = psel & 7;
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grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
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mmcr1 |= (u64)grsel << grsel_shift[bit];
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mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
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}
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if (power5_marked_instr_event(event[i]))
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mmcra |= MMCRA_SAMPLE_ENABLE;
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@@ -541,7 +544,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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return 0;
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}
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static void power5_disable_pmc(unsigned int pmc, u64 mmcr[])
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static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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{
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if (pmc <= 3)
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mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
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@@ -597,15 +600,15 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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};
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struct power_pmu power5_pmu = {
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.n_counter = 6,
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.max_alternatives = MAX_ALT,
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.add_fields = 0x7000090000555ull,
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.test_adder = 0x3000490000000ull,
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.compute_mmcr = power5_compute_mmcr,
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.get_constraint = power5_get_constraint,
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.get_alternatives = power5_get_alternatives,
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.disable_pmc = power5_disable_pmc,
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.n_generic = ARRAY_SIZE(power5_generic_events),
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.generic_events = power5_generic_events,
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.cache_events = &power5_cache_events,
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.n_counter = 6,
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.max_alternatives = MAX_ALT,
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.add_fields = 0x7000090000555ul,
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.test_adder = 0x3000490000000ul,
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.compute_mmcr = power5_compute_mmcr,
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.get_constraint = power5_get_constraint,
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.get_alternatives = power5_get_alternatives,
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.disable_pmc = power5_disable_pmc,
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.n_generic = ARRAY_SIZE(power5_generic_events),
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.generic_events = power5_generic_events,
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.cache_events = &power5_cache_events,
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};
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