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drm/amdgpu: use direct loading on renoir vcn for the moment

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PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use
direct loading for the moment till the issue is addressed.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Este commit está contenido en:
Huang Rui
2019-07-21 20:58:31 +08:00
cometido por Alex Deucher
padre 8deac23636
commit 444a0fea51
Se han modificado 2 ficheros con 12 adiciones y 6 borrados
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9
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
Ver fichero

@@ -100,7 +100,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
case CHIP_NAVI14:
fw_name = FIRMWARE_NAVI14;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
adev->asic_type != CHIP_RENOIR) /* to be removed while vcn psp loading works */
adev->vcn.indirect_sram = true;
break;
case CHIP_NAVI12:
@@ -160,7 +161,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
adev->asic_type == CHIP_RENOIR)
bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@@ -271,7 +273,8 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
unsigned offset;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
adev->asic_type == CHIP_RENOIR) {
offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
le32_to_cpu(hdr->ucode_size_bytes));

9
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
Ver fichero

@@ -142,7 +142,8 @@ static int vcn_v2_0_sw_init(void *handle)
if (r)
return r;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
adev->asic_type != CHIP_RENOIR) {
const struct common_firmware_header *hdr;
hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
@@ -366,7 +367,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
uint32_t offset;
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
adev->asic_type != CHIP_RENOIR) {
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -411,7 +413,8 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
uint32_t offset;
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
adev->asic_type != CHIP_RENOIR) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),