Merge tag 'timers-core-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
"Time, timers and related driver updates:
- Prevent unnecessary timer softirq invocations by extending the
tracking of the next expiring timer in the timer wheel beyond the
existing NOHZ functionality.
The tracking overhead at enqueue time is within the noise, but on
sensitive workloads the avoidance of the soft interrupt invocation
is a measurable improvement.
- The obligatory new clocksource driver for Ingenic X100 OST
- The usual fixes, improvements, cleanups and extensions for newer
chip variants all over the driver space"
* tag 'timers-core-2020-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (28 commits)
timers: Recalculate next timer interrupt only when necessary
clocksource/drivers/ingenic: Add support for the Ingenic X1000 OST.
dt-bindings: timer: Add Ingenic X1000 OST bindings.
clocksource/drivers: Replace HTTP links with HTTPS ones
clocksource/drivers/nomadik-mtu: Handle 32kHz clock
clocksource/drivers/sh_cmt: Use "kHz" for kilohertz
clocksource/drivers/imx: Add support for i.MX TPM driver with ARM64
clocksource/drivers/ingenic: Add high resolution timer support for SMP/SMT.
timers: Lower base clock forwarding threshold
timers: Remove must_forward_clk
timers: Spare timer softirq until next expiry
timers: Expand clk forward logic beyond nohz
timers: Reuse next expiry cache after nohz exit
timers: Always keep track of next expiry
timers: Optimize _next_timer_interrupt() level iteration
timers: Add comments about calc_index() ceiling work
timers: Move trigger_dyntick_cpu() to enqueue_timer()
timers: Use only bucket expiry for base->next_expiry value
timers: Preserve higher bits of expiration on index calculation
clocksource/drivers/timer-atmel-tcb: Add sama5d2 support
...
This commit is contained in:
Linus Torvalds
@@ -1,56 +0,0 @@
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* Device tree bindings for Atmel Timer Counter Blocks
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- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
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<chip> can be "at91rm9200" or "at91sam9x5"
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- reg: Should contain registers location and length
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- #address-cells: has to be 1
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- #size-cells: has to be 0
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- interrupts: Should contain all interrupts for the TC block
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Note that you can specify several interrupt cells if the TC
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block has one interrupt per channel.
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- clock-names: tuple listing input clock names.
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Required elements: "t0_clk", "slow_clk"
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Optional elements: "t1_clk", "t2_clk"
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- clocks: phandles to input clocks.
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The TCB can expose multiple subdevices:
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* a timer
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- compatible: Should be "atmel,tcb-timer"
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- reg: Should contain the TCB channels to be used. If the
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counter width is 16 bits (at91rm9200-tcb), two consecutive
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channels are needed. Else, only one channel will be used.
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Examples:
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One interrupt per TC block:
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tcb0: timer@fff7c000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff7c000 0x100>;
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interrupts = <18 4>;
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clocks = <&tcb0_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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timer@0 {
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compatible = "atmel,tcb-timer";
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reg = <0>, <1>;
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};
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timer@2 {
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compatible = "atmel,tcb-timer";
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reg = <2>;
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};
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};
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One interrupt per TC channel in a TC block:
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tcb1: timer@fffdc000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfffdc000 0x100>;
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interrupts = <26 4>, <27 4>, <28 4>;
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clocks = <&tcb1_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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};
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@@ -0,0 +1,155 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Atmel Timer Counter Block
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maintainers:
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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description: |
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The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
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timer has three channels with two counters each.
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properties:
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compatible:
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items:
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- enum:
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- atmel,at91rm9200-tcb
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- atmel,at91sam9x5-tcb
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- atmel,sama5d2-tcb
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- const: simple-mfd
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- const: syscon
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reg:
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maxItems: 1
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interrupts:
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description:
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List of interrupts. One interrupt per TCB channel if available or one
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interrupt for the TC block
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minItems: 1
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maxItems: 3
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clock-names:
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description:
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List of clock names. Always includes t0_clk and slow clk. Also includes
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t1_clk and t2_clk if a clock per channel is available.
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minItems: 2
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maxItems: 4
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clocks:
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minItems: 2
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maxItems: 4
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^timer@[0-2]$":
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description: The timer block channels that are used as timers.
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type: object
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properties:
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compatible:
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const: atmel,tcb-timer
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reg:
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description:
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List of channels to use for this particular timer.
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minItems: 1
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maxItems: 3
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required:
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- compatible
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: atmel,sama5d2-tcb
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: t0_clk
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- const: gclk
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- const: slow_clk
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else:
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properties:
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clocks:
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minItems: 2
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maxItems: 4
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clock-names:
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oneOf:
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- items:
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- const: t0_clk
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- const: slow_clk
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- items:
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- const: t0_clk
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- const: t1_clk
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- const: t2_clk
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- const: slow_clk
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- '#address-cells'
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- '#size-cells'
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additionalProperties: false
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examples:
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- |
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/* One interrupt per TC block: */
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tcb0: timer@fff7c000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff7c000 0x100>;
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interrupts = <18 4>;
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clocks = <&tcb0_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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timer@0 {
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compatible = "atmel,tcb-timer";
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reg = <0>, <1>;
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};
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timer@2 {
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compatible = "atmel,tcb-timer";
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reg = <2>;
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};
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};
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/* One interrupt per TC channel in a TC block: */
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tcb1: timer@fffdc000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfffdc000 0x100>;
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interrupts = <26 4>, <27 4>, <28 4>;
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clocks = <&tcb1_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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timer@0 {
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compatible = "atmel,tcb-timer";
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reg = <0>;
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};
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timer@1 {
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compatible = "atmel,tcb-timer";
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reg = <1>;
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};
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};
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63
Documentation/devicetree/bindings/timer/ingenic,sysost.yaml
Normal file
63
Documentation/devicetree/bindings/timer/ingenic,sysost.yaml
Normal file
@@ -0,0 +1,63 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/ingenic,sysost.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bindings for SYSOST in Ingenic XBurst family SoCs
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maintainers:
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- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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description:
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The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource
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and one or more 32bit timers for clockevent.
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properties:
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"#clock-cells":
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const: 1
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compatible:
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enum:
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- ingenic,x1000-ost
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- ingenic,x2000-ost
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: ost
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interrupts:
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maxItems: 1
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required:
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- "#clock-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/x1000-cgu.h>
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ost: timer@12000000 {
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compatible = "ingenic,x1000-ost";
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reg = <0x12000000 0x3c>;
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#clock-cells = <1>;
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clocks = <&cgu X1000_CLK_OST>;
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clock-names = "ost";
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interrupt-parent = <&cpuintc>;
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interrupts = <3>;
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};
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...
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@@ -10,7 +10,7 @@ It is global timer is a free running up-counter and can generate interrupt
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when the counter reaches preset counter values.
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Documentation:
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http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
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https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
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Required properties:
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