Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS updates from Thomas Gleixner: "The RAS updates for the 4.13 merge window: - Cleanup of the MCE injection facility (Borsilav Petkov) - Rework of the AMD/SMCA handling (Yazen Ghannam) - Enhancements for ACPI/APEI to handle new notitication types (Shiju Jose) - atomic_t to refcount_t conversion (Elena Reshetova) - A few fixes and enhancements all over the place" * 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: RAS/CEC: Check the correct variable in the debugfs error handling x86/mce: Always save severity in machine_check_poll() x86/MCE, xen/mcelog: Make /dev/mcelog registration messages more precise x86/mce: Update bootlog description to reflect behavior on AMD x86/mce: Don't disable MCA banks when offlining a CPU on AMD x86/mce/mce-inject: Preset the MCE injection struct x86/mce: Clean up include files x86/mce: Get rid of register_mce_write_callback() x86/mce: Merge mce_amd_inj into mce-inject x86/mce/AMD: Use saved threshold block info in interrupt handler x86/mce/AMD: Use msr_stat when clearing MCA_STATUS x86/mce/AMD: Carve out SMCA bank configuration x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers x86/mce: Convert threshold_bank.cpus from atomic_t to refcount_t RAS: Make local function parse_ras_param() static ACPI/APEI: Handle GSIV and GPIO notification types
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@@ -3,6 +3,7 @@
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/refcount.h>
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struct amd_nb_bus_dev_range {
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u8 bus;
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@@ -55,7 +56,7 @@ struct threshold_bank {
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struct threshold_block *blocks;
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/* initialized to the number of CPUs on the node sharing this bank */
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atomic_t cpus;
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refcount_t cpus;
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};
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struct amd_northbridge {
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@@ -285,10 +285,6 @@ int mce_notify_irq(void);
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DECLARE_PER_CPU(struct mce, injectm);
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extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off));
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/* Disable CMCI/polling for MCA bank claimed by firmware */
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extern void mce_disable_bank(int bank);
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@@ -907,8 +907,13 @@ static inline int mpx_disable_management(void)
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}
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#endif /* CONFIG_X86_INTEL_MPX */
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#ifdef CONFIG_CPU_SUP_AMD
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extern u16 amd_get_nb_id(int cpu);
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extern u32 amd_get_nodes_per_socket(void);
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#else
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static inline u16 amd_get_nb_id(int cpu) { return 0; }
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static inline u32 amd_get_nodes_per_socket(void) { return 0; }
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#endif
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static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
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{
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