Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King: - add support for ELF fdpic binaries on both MMU and noMMU platforms - linker script cleanups - support for compressed .data section for XIP images - discard memblock arrays when possible - various cleanups - atomic DMA pool updates - better diagnostics of missing/corrupt device tree - export information to allow userspace kexec tool to place images more inteligently, so that the device tree isn't overwritten by the booting kernel - make early_printk more efficient on semihosted systems - noMMU cleanups - SA1111 PCMCIA update in preparation for further cleanups * 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (38 commits) ARM: 8719/1: NOMMU: work around maybe-uninitialized warning ARM: 8717/2: debug printch/printascii: translate '\n' to "\r\n" not "\n\r" ARM: 8713/1: NOMMU: Support MPU in XIP configuration ARM: 8712/1: NOMMU: Use more MPU regions to cover memory ARM: 8711/1: V7M: Add support for MPU to M-class ARM: 8710/1: Kconfig: Kill CONFIG_VECTORS_BASE ARM: 8709/1: NOMMU: Disallow MPU for XIP ARM: 8708/1: NOMMU: Rework MPU to be mostly done in C ARM: 8707/1: NOMMU: Update MPU accessors to use cp15 helpers ARM: 8706/1: NOMMU: Move out MPU setup in separate module ARM: 8702/1: head-common.S: Clear lr before jumping to start_kernel() ARM: 8705/1: early_printk: use printascii() rather than printch() ARM: 8703/1: debug.S: move hexbuf to a writable section ARM: add additional table to compressed kernel ARM: decompressor: fix BSS size calculation pcmcia: sa1111: remove special sa1111 mmio accessors pcmcia: sa1111: use sa1111_get_irq() to obtain IRQ resources ARM: better diagnostics with missing/corrupt dtb ARM: 8699/1: dma-mapping: Remove init_dma_coherent_pool_size() ARM: 8698/1: dma-mapping: Mark atomic_pool as __ro_after_init ..
This commit is contained in:
Linus Torvalds
@@ -7,6 +7,8 @@
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/* No __ro_after_init data in the .rodata section - which will always be ro */
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#define RO_AFTER_INIT_DATA
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#include <linux/sizes.h>
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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@@ -78,9 +80,7 @@ SECTIONS
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*(.text.fixup)
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*(__ex_table)
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#endif
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#ifndef CONFIG_SMP_ON_UP
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*(.alt.smp.init)
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#endif
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*(.discard)
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*(.discard.*)
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}
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@@ -182,19 +182,7 @@ SECTIONS
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*(.taglist.init)
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__tagtable_end = .;
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}
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#ifdef CONFIG_SMP_ON_UP
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.init.smpalt : {
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__smpalt_begin = .;
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*(.alt.smp.init)
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__smpalt_end = .;
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}
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#endif
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.init.pv_table : {
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__pv_table_begin = .;
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*(.pv_table)
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__pv_table_end = .;
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}
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.init.data : {
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.init.rodata : {
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INIT_SETUP(16)
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INIT_CALLS
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CON_INITCALL
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@@ -202,48 +190,49 @@ SECTIONS
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INIT_RAM_FS
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}
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#ifdef CONFIG_ARM_MPU
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. = ALIGN(SZ_128K);
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#endif
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_exiprom = .; /* End of XIP ROM area */
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/*
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* From this point, stuff is considered writable and will be copied to RAM
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*/
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__data_loc = ALIGN(4); /* location in file */
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. = PAGE_OFFSET + TEXT_OFFSET; /* location in memory */
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#undef LOAD_OFFSET
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#define LOAD_OFFSET (PAGE_OFFSET + TEXT_OFFSET - __data_loc)
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. = ALIGN(THREAD_SIZE);
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_sdata = .;
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RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
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.data.ro_after_init : AT(ADDR(.data.ro_after_init) - LOAD_OFFSET) {
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*(.data..ro_after_init)
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}
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_edata = .;
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. = ALIGN(PAGE_SIZE);
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__init_begin = .;
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.init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
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INIT_DATA
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}
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.exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
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ARM_EXIT_KEEP(EXIT_DATA)
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}
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#ifdef CONFIG_SMP
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PERCPU_SECTION(L1_CACHE_BYTES)
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#endif
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_exiprom = .; /* End of XIP ROM area */
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__data_loc = ALIGN(4); /* location in binary */
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. = PAGE_OFFSET + TEXT_OFFSET;
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/*
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* End of copied data. We need a dummy section to get its LMA.
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* Also located before final ALIGN() as trailing padding is not stored
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* in the resulting binary file and useless to copy.
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*/
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.data.endmark : AT(ADDR(.data.endmark) - LOAD_OFFSET) { }
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_edata_loc = LOADADDR(.data.endmark);
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.data : AT(__data_loc) {
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_data = .; /* address in memory */
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_sdata = .;
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/*
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* first, the init task union, aligned
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* to an 8192 byte boundary.
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*/
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INIT_TASK_DATA(THREAD_SIZE)
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. = ALIGN(PAGE_SIZE);
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__init_begin = .;
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INIT_DATA
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ARM_EXIT_KEEP(EXIT_DATA)
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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*(.data..ro_after_init)
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NOSAVE_DATA
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CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
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READ_MOSTLY_DATA(L1_CACHE_BYTES)
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/*
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* and the usual data section
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*/
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DATA_DATA
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CONSTRUCTORS
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_edata = .;
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}
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_edata_loc = __data_loc + SIZEOF(.data);
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BUG_TABLE
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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#ifdef CONFIG_HAVE_TCM
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/*
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@@ -302,7 +291,7 @@ SECTIONS
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}
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#endif
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BSS_SECTION(0, 0, 0)
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BSS_SECTION(0, 0, 8)
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_end = .;
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STABS_DEBUG
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@@ -323,3 +312,29 @@ ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
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*/
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ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & PAGE_MASK) <= PAGE_SIZE,
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"HYP init code too big or misaligned")
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#ifdef CONFIG_XIP_DEFLATED_DATA
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/*
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* The .bss is used as a stack area for __inflate_kernel_data() whose stack
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* frame is 9568 bytes. Make sure it has extra room left.
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*/
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ASSERT((_end - __bss_start) >= 12288, ".bss too small for CONFIG_XIP_DEFLATED_DATA")
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#endif
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#ifdef CONFIG_ARM_MPU
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/*
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* Due to PMSAv7 restriction on base address and size we have to
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* enforce minimal alignment restrictions. It was seen that weaker
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* alignment restriction on _xiprom will likely force XIP address
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* space spawns multiple MPU regions thus it is likely we run in
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* situation when we are reprogramming MPU region we run on with
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* something which doesn't cover reprogramming code itself, so as soon
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* as we update MPU settings we'd immediately try to execute straight
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* from background region which is XN.
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* It seem that alignment in 1M should suit most users.
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* _exiprom is aligned as 1/8 of 1M so can be covered by subregion
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* disable
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*/
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ASSERT(!(_xiprom & (SZ_1M - 1)), "XIP start address may cause MPU programming issues")
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ASSERT(!(_exiprom & (SZ_128K - 1)), "XIP end address may cause MPU programming issues")
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#endif
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