ARM: dts: turris-omnia: Fix mpp26 pin name and comment
[ Upstream commit 49e93898f0dc177e645c22d0664813567fd9ec00 ]
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
which is routed to CN11 pin header, is documented as SPI CS1, but
MPP[26] pin does not support this function. Instead it controls chip
select 2 if in "spi0" mode.
Fix the name of the pin node in pinctrl node and fix the comment in SPI
node.
Fixes: 26ca8b52d6
("ARM: dts: add support for Turris Omnia")
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:

committed by
Greg Kroah-Hartman

parent
d5c2051898
commit
43faaedf3a
@@ -307,7 +307,7 @@
|
|||||||
marvell,function = "spi0";
|
marvell,function = "spi0";
|
||||||
};
|
};
|
||||||
|
|
||||||
spi0cs1_pins: spi0cs1-pins {
|
spi0cs2_pins: spi0cs2-pins {
|
||||||
marvell,pins = "mpp26";
|
marvell,pins = "mpp26";
|
||||||
marvell,function = "spi0";
|
marvell,function = "spi0";
|
||||||
};
|
};
|
||||||
@@ -342,7 +342,7 @@
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
|
/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
|
||||||
};
|
};
|
||||||
|
|
||||||
&uart0 {
|
&uart0 {
|
||||||
|
Reference in New Issue
Block a user