Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs. A slew of changes this release cycle. The reset driver tree, that we merge through arm-soc for historical reasons, is also sizable this time around. Among the changes: - clps711x: Treewide changes to compatible strings, merged here for simplicity. - Qualcomm: SCM firmware driver cleanups, move to platform driver - ux500: Major cleanups, removal of old mach-specific infrastructure. - Atmel external bus memory driver - Move of brcmstb platform to the rest of bcm - PMC driver updates for tegra, various fixes and improvements - Samsung platform driver updates to support 64-bit Exynos platforms - Reset controller cleanups moving to devm_reset_controller_register() APIs - Reset controller driver for Amlogic Meson - Reset controller driver for Hisilicon hi6220 - ARM SCPI power domain support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits) ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data soc: raspberrypi-power: add CONFIG_OF dependency firmware: scpi: add CONFIG_OF dependency video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip pwm: clps711x: Changing the compatibility string to match with the smallest supported chip serial: clps711x: Changing the compatibility string to match with the smallest supported chip irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip clk: clps711x: Changing the compatibility string to match with the smallest supported chip ...
This commit is contained in:
Linus Torvalds
210
include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
Normal file
210
include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
Normal file
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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||||
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||||
/* RESET0 */
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||||
#define RESET_HIU 0
|
||||
/* 1 */
|
||||
#define RESET_DOS_RESET 2
|
||||
#define RESET_DDR_TOP 3
|
||||
#define RESET_DCU_RESET 4
|
||||
#define RESET_VIU 5
|
||||
#define RESET_AIU 6
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||||
#define RESET_VID_PLL_DIV 7
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||||
/* 8 */
|
||||
#define RESET_PMUX 9
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||||
#define RESET_VENC 10
|
||||
#define RESET_ASSIST 11
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||||
#define RESET_AFIFO2 12
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||||
#define RESET_VCBUS 13
|
||||
/* 14 */
|
||||
/* 15 */
|
||||
#define RESET_GIC 16
|
||||
#define RESET_CAPB3_DECODE 17
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||||
#define RESET_NAND_CAPB3 18
|
||||
#define RESET_HDMITX_CAPB3 19
|
||||
#define RESET_MALI_CAPB3 20
|
||||
#define RESET_DOS_CAPB3 21
|
||||
#define RESET_SYS_CPU_CAPB3 22
|
||||
#define RESET_CBUS_CAPB3 23
|
||||
#define RESET_AHB_CNTL 24
|
||||
#define RESET_AHB_DATA 25
|
||||
#define RESET_VCBUS_CLK81 26
|
||||
#define RESET_MMC 27
|
||||
#define RESET_MIPI_0 28
|
||||
#define RESET_MIPI_1 29
|
||||
#define RESET_MIPI_2 30
|
||||
#define RESET_MIPI_3 31
|
||||
/* RESET1 */
|
||||
#define RESET_CPPM 32
|
||||
#define RESET_DEMUX 33
|
||||
#define RESET_USB_OTG 34
|
||||
#define RESET_DDR 35
|
||||
#define RESET_AO_RESET 36
|
||||
#define RESET_BT656 37
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#define RESET_AHB_SRAM 38
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/* 39 */
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#define RESET_PARSER 40
|
||||
#define RESET_BLKMV 41
|
||||
#define RESET_ISA 42
|
||||
#define RESET_ETHERNET 43
|
||||
#define RESET_SD_EMMC_A 44
|
||||
#define RESET_SD_EMMC_B 45
|
||||
#define RESET_SD_EMMC_C 46
|
||||
#define RESET_ROM_BOOT 47
|
||||
#define RESET_SYS_CPU_0 48
|
||||
#define RESET_SYS_CPU_1 49
|
||||
#define RESET_SYS_CPU_2 50
|
||||
#define RESET_SYS_CPU_3 51
|
||||
#define RESET_SYS_CPU_CORE_0 52
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||||
#define RESET_SYS_CPU_CORE_1 53
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||||
#define RESET_SYS_CPU_CORE_2 54
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||||
#define RESET_SYS_CPU_CORE_3 55
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||||
#define RESET_SYS_PLL_DIV 56
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||||
#define RESET_SYS_CPU_AXI 57
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||||
#define RESET_SYS_CPU_L2 58
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||||
#define RESET_SYS_CPU_P 59
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||||
#define RESET_SYS_CPU_MBIST 60
|
||||
/* 61 */
|
||||
/* 62 */
|
||||
/* 63 */
|
||||
/* RESET2 */
|
||||
#define RESET_VD_RMEM 64
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||||
#define RESET_AUDIN 65
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||||
#define RESET_HDMI_TX 66
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||||
/* 67 */
|
||||
/* 68 */
|
||||
/* 69 */
|
||||
#define RESET_GE2D 70
|
||||
#define RESET_PARSER_REG 71
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||||
#define RESET_PARSER_FETCH 72
|
||||
#define RESET_PARSER_CTL 73
|
||||
#define RESET_PARSER_TOP 74
|
||||
/* 75 */
|
||||
/* 76 */
|
||||
#define RESET_AO_CPU_RESET 77
|
||||
#define RESET_MALI 78
|
||||
#define RESET_HDMI_SYSTEM_RESET 79
|
||||
/* 80-95 */
|
||||
/* RESET3 */
|
||||
#define RESET_RING_OSCILLATOR 96
|
||||
#define RESET_SYS_CPU 97
|
||||
#define RESET_EFUSE 98
|
||||
#define RESET_SYS_CPU_BVCI 99
|
||||
#define RESET_AIFIFO 100
|
||||
#define RESET_TVFE 101
|
||||
#define RESET_AHB_BRIDGE_CNTL 102
|
||||
/* 103 */
|
||||
#define RESET_AUDIO_DAC 104
|
||||
#define RESET_DEMUX_TOP 105
|
||||
#define RESET_DEMUX_DES 106
|
||||
#define RESET_DEMUX_S2P_0 107
|
||||
#define RESET_DEMUX_S2P_1 108
|
||||
#define RESET_DEMUX_RESET_0 109
|
||||
#define RESET_DEMUX_RESET_1 110
|
||||
#define RESET_DEMUX_RESET_2 111
|
||||
/* 112-127 */
|
||||
/* RESET4 */
|
||||
/* 128 */
|
||||
/* 129 */
|
||||
/* 130 */
|
||||
/* 131 */
|
||||
#define RESET_DVIN_RESET 132
|
||||
#define RESET_RDMA 133
|
||||
#define RESET_VENCI 134
|
||||
#define RESET_VENCP 135
|
||||
/* 136 */
|
||||
#define RESET_VDAC 137
|
||||
#define RESET_RTC 138
|
||||
/* 139 */
|
||||
#define RESET_VDI6 140
|
||||
#define RESET_VENCL 141
|
||||
#define RESET_I2C_MASTER_2 142
|
||||
#define RESET_I2C_MASTER_1 143
|
||||
/* 144-159 */
|
||||
/* RESET5 */
|
||||
/* 160-191 */
|
||||
/* RESET6 */
|
||||
#define RESET_PERIPHS_GENERAL 192
|
||||
#define RESET_PERIPHS_SPICC 193
|
||||
#define RESET_PERIPHS_SMART_CARD 194
|
||||
#define RESET_PERIPHS_SAR_ADC 195
|
||||
#define RESET_PERIPHS_I2C_MASTER_0 196
|
||||
#define RESET_SANA 197
|
||||
/* 198 */
|
||||
#define RESET_PERIPHS_STREAM_INTERFACE 199
|
||||
#define RESET_PERIPHS_SDIO 200
|
||||
#define RESET_PERIPHS_UART_0 201
|
||||
#define RESET_PERIPHS_UART_1_2 202
|
||||
#define RESET_PERIPHS_ASYNC_0 203
|
||||
#define RESET_PERIPHS_ASYNC_1 204
|
||||
#define RESET_PERIPHS_SPI_0 205
|
||||
#define RESET_PERIPHS_SDHC 206
|
||||
#define RESET_UART_SLIP 207
|
||||
/* 208-223 */
|
||||
/* RESET7 */
|
||||
#define RESET_USB_DDR_0 224
|
||||
#define RESET_USB_DDR_1 225
|
||||
#define RESET_USB_DDR_2 226
|
||||
#define RESET_USB_DDR_3 227
|
||||
/* 228 */
|
||||
#define RESET_DEVICE_MMC_ARB 229
|
||||
/* 230 */
|
||||
#define RESET_VID_LOCK 231
|
||||
#define RESET_A9_DMC_PIPEL 232
|
||||
/* 233-255 */
|
||||
|
||||
#endif
|
||||
175
include/dt-bindings/reset/amlogic,meson8b-reset.h
Normal file
175
include/dt-bindings/reset/amlogic,meson8b-reset.h
Normal file
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
#define RESET_HIU 0
|
||||
#define RESET_VLD 1
|
||||
#define RESET_IQIDCT 2
|
||||
#define RESET_MC 3
|
||||
/* 8 */
|
||||
#define RESET_VIU 5
|
||||
#define RESET_AIU 6
|
||||
#define RESET_MCPU 7
|
||||
#define RESET_CCPU 8
|
||||
#define RESET_PMUX 9
|
||||
#define RESET_VENC 10
|
||||
#define RESET_ASSIST 11
|
||||
#define RESET_AFIFO2 12
|
||||
#define RESET_MDEC 13
|
||||
#define RESET_VLD_PART 14
|
||||
#define RESET_VIFIFO 15
|
||||
/* 16-31 */
|
||||
/* RESET1 */
|
||||
/* 32 */
|
||||
#define RESET_DEMUX 33
|
||||
#define RESET_USB_OTG 34
|
||||
#define RESET_DDR 35
|
||||
#define RESET_VDAC_1 36
|
||||
#define RESET_BT656 37
|
||||
#define RESET_AHB_SRAM 38
|
||||
#define RESET_AHB_BRIDGE 39
|
||||
#define RESET_PARSER 40
|
||||
#define RESET_BLKMV 41
|
||||
#define RESET_ISA 42
|
||||
#define RESET_ETHERNET 43
|
||||
#define RESET_ABUF 44
|
||||
#define RESET_AHB_DATA 45
|
||||
#define RESET_AHB_CNTL 46
|
||||
#define RESET_ROM_BOOT 47
|
||||
/* 48-63 */
|
||||
/* RESET2 */
|
||||
#define RESET_VD_RMEM 64
|
||||
#define RESET_AUDIN 65
|
||||
#define RESET_DBLK 66
|
||||
#define RESET_PIC_DC 66
|
||||
#define RESET_PSC 66
|
||||
#define RESET_NAND 66
|
||||
#define RESET_GE2D 70
|
||||
#define RESET_PARSER_REG 71
|
||||
#define RESET_PARSER_FETCH 72
|
||||
#define RESET_PARSER_CTL 73
|
||||
#define RESET_PARSER_TOP 74
|
||||
#define RESET_HDMI_APB 75
|
||||
#define RESET_AUDIO_APB 76
|
||||
#define RESET_MEDIA_CPU 77
|
||||
#define RESET_MALI 78
|
||||
#define RESET_HDMI_SYSTEM_RESET 79
|
||||
/* 80-95 */
|
||||
/* RESET3 */
|
||||
#define RESET_RING_OSCILLATOR 96
|
||||
#define RESET_SYS_CPU_0 97
|
||||
#define RESET_EFUSE 98
|
||||
#define RESET_SYS_CPU_BVCI 99
|
||||
#define RESET_AIFIFO 100
|
||||
#define RESET_AUDIO_PLL_MODULATOR 101
|
||||
#define RESET_AHB_BRIDGE_CNTL 102
|
||||
#define RESET_SYS_CPU_1 103
|
||||
#define RESET_AUDIO_DAC 104
|
||||
#define RESET_DEMUX_TOP 105
|
||||
#define RESET_DEMUX_DES 106
|
||||
#define RESET_DEMUX_S2P_0 107
|
||||
#define RESET_DEMUX_S2P_1 108
|
||||
#define RESET_DEMUX_RESET_0 109
|
||||
#define RESET_DEMUX_RESET_1 110
|
||||
#define RESET_DEMUX_RESET_2 111
|
||||
/* 112-127 */
|
||||
/* RESET4 */
|
||||
#define RESET_PL310 128
|
||||
#define RESET_A5_APB 129
|
||||
#define RESET_A5_AXI 130
|
||||
#define RESET_A5 131
|
||||
#define RESET_DVIN 132
|
||||
#define RESET_RDMA 133
|
||||
#define RESET_VENCI 134
|
||||
#define RESET_VENCP 135
|
||||
#define RESET_VENCT 136
|
||||
#define RESET_VDAC_4 137
|
||||
#define RESET_RTC 138
|
||||
#define RESET_A5_DEBUG 139
|
||||
#define RESET_VDI6 140
|
||||
#define RESET_VENCL 141
|
||||
/* 142-159 */
|
||||
/* RESET5 */
|
||||
#define RESET_DDR_PLL 160
|
||||
#define RESET_MISC_PLL 161
|
||||
#define RESET_SYS_PLL 162
|
||||
#define RESET_HPLL_PLL 163
|
||||
#define RESET_AUDIO_PLL 164
|
||||
#define RESET_VID2_PLL 165
|
||||
/* 166-191 */
|
||||
/* RESET6 */
|
||||
#define RESET_PERIPHS_GENERAL 192
|
||||
#define RESET_PERIPHS_IR_REMOTE 193
|
||||
#define RESET_PERIPHS_SMART_CARD 194
|
||||
#define RESET_PERIPHS_SAR_ADC 195
|
||||
#define RESET_PERIPHS_I2C_MASTER_0 196
|
||||
#define RESET_PERIPHS_I2C_MASTER_1 197
|
||||
#define RESET_PERIPHS_I2C_SLAVE 198
|
||||
#define RESET_PERIPHS_STREAM_INTERFACE 199
|
||||
#define RESET_PERIPHS_SDIO 200
|
||||
#define RESET_PERIPHS_UART_0 201
|
||||
#define RESET_PERIPHS_UART_1 202
|
||||
#define RESET_PERIPHS_ASYNC_0 203
|
||||
#define RESET_PERIPHS_ASYNC_1 204
|
||||
#define RESET_PERIPHS_SPI_0 205
|
||||
#define RESET_PERIPHS_SPI_1 206
|
||||
#define RESET_PERIPHS_LED_PWM 207
|
||||
/* 208-223 */
|
||||
/* RESET7 */
|
||||
/* 224-255 */
|
||||
|
||||
#endif
|
||||
@@ -64,4 +64,12 @@
|
||||
#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
|
||||
#define PERIPH_RSDIST9_CARM_ETM 0x508
|
||||
|
||||
#define MEDIA_G3D 0
|
||||
#define MEDIA_CODEC_VPU 2
|
||||
#define MEDIA_CODEC_JPEG 3
|
||||
#define MEDIA_ISP 4
|
||||
#define MEDIA_ADE 5
|
||||
#define MEDIA_MMU 6
|
||||
#define MEDIA_XG2RAM1 7
|
||||
|
||||
#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
|
||||
|
||||
38
include/dt-bindings/reset/ti-syscon.h
Normal file
38
include/dt-bindings/reset/ti-syscon.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* TI Syscon Reset definitions
|
||||
*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
|
||||
#define __DT_BINDINGS_RESET_TI_SYSCON_H__
|
||||
|
||||
/*
|
||||
* The reset does not support the feature and corresponding
|
||||
* values are not valid
|
||||
*/
|
||||
#define ASSERT_NONE (1 << 0)
|
||||
#define DEASSERT_NONE (1 << 1)
|
||||
#define STATUS_NONE (1 << 2)
|
||||
|
||||
/* When set this function is activated by setting(vs clearing) this bit */
|
||||
#define ASSERT_SET (1 << 3)
|
||||
#define DEASSERT_SET (1 << 4)
|
||||
#define STATUS_SET (1 << 5)
|
||||
|
||||
/* The following are the inverse of the above and are added for consistency */
|
||||
#define ASSERT_CLEAR (0 << 3)
|
||||
#define DEASSERT_CLEAR (0 << 4)
|
||||
#define STATUS_CLEAR (0 << 5)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user