arm64: KVM: Enable VHE support for :G/:H perf event modifiers
With VHE different exception levels are used between the host (EL2) and guest (EL1) with a shared exception level for userpace (EL0). We can take advantage of this and use the PMU's exception level filtering to avoid enabling/disabling counters in the world-switch code. Instead we just modify the counter type to include or exclude EL0 at vcpu_{load,put} time. We also ensure that trapped PMU system register writes do not re-enable EL0 when reconfiguring the backing perf events. This approach completely avoids blackout windows seen with !VHE. Suggested-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Marc Zyngier

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@@ -368,6 +368,9 @@ static inline void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arm_vhe_guest_enter(void) {}
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static inline void kvm_arm_vhe_guest_exit(void) {}
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