[MIPS] New files for lemote fulong mini-PC support
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Songmao Tian <tiansm@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Songmao Tian
committed by
Ralf Baechle
Ralf Baechle
parent
2a21c7300b
commit
42d226c724
@@ -28,6 +28,7 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
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obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
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obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
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obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
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obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
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obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
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obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
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obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
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242
arch/mips/pci/fixup-lm2e.c
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242
arch/mips/pci/fixup-lm2e.c
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@@ -0,0 +1,242 @@
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/*
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* fixup-lm2e.c
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*
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* Copyright (C) 2004 ICT CAS
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* Author: Li xiaoyu, ICT CAS
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* lixy@ict.ac.cn
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*
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* Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/mips-boards/bonito64.h>
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/* South bridge slot number is set by the pci probe process */
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static u8 sb_slot = 5;
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = 0;
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if (slot == sb_slot) {
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switch (PCI_FUNC(dev->devfn)) {
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case 2:
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irq = 10;
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break;
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case 3:
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irq = 11;
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break;
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case 5:
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irq = 9;
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break;
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}
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} else {
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irq = BONITO_IRQ_BASE + 25 + pin;
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}
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return irq;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
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{
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unsigned int val;
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/* Configues port 1, 2, 3, 4 to be validate*/
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pci_read_config_dword(pdev, 0xe0, &val);
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pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4);
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/* System clock is 48-MHz Oscillator. */
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pci_write_config_dword(pdev, 0xe4, 1 << 5);
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}
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static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
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{
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unsigned char c;
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sb_slot = PCI_SLOT(pdev->devfn);
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printk(KERN_INFO "via686b fix: ISA bridge\n");
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/* Enable I/O Recovery time */
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pci_write_config_byte(pdev, 0x40, 0x08);
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/* Enable ISA refresh */
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pci_write_config_byte(pdev, 0x41, 0x01);
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/* disable ISA line buffer */
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pci_write_config_byte(pdev, 0x45, 0x00);
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/* Gate INTR, and flush line buffer */
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pci_write_config_byte(pdev, 0x46, 0xe0);
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/* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */
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/* pci_write_config_byte(pdev, 0x47, 0x20); */
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/*
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* enable PCI Delay Transaction, Enable EISA ports 4D0/4D1.
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* enable time-out timer
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*/
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pci_write_config_byte(pdev, 0x47, 0xe6);
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/*
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* enable level trigger on pci irqs: 9,10,11,13
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* important! without this PCI interrupts won't work
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*/
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outb(0x2e, 0x4d1);
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/* 512 K PCI Decode */
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pci_write_config_byte(pdev, 0x48, 0x01);
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/* Wait for PGNT before grant to ISA Master/DMA */
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pci_write_config_byte(pdev, 0x4a, 0x84);
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/*
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* Plug'n'Play
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*
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* Parallel DRQ 3, Floppy DRQ 2 (default)
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*/
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pci_write_config_byte(pdev, 0x50, 0x0e);
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/*
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* IRQ Routing for Floppy and Parallel port
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*
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* IRQ 6 for floppy, IRQ 7 for parallel port
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*/
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pci_write_config_byte(pdev, 0x51, 0x76);
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/* IRQ Routing for serial ports (take IRQ 3 and 4) */
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pci_write_config_byte(pdev, 0x52, 0x34);
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/* All IRQ's level triggered. */
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pci_write_config_byte(pdev, 0x54, 0x00);
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/* route PIRQA-D irq */
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pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */
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pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */
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/* 3-0, PIRQB */
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pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */
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/* enable function 5/6, audio/modem */
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pci_read_config_byte(pdev, 0x85, &c);
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c &= ~(0x3 << 2);
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pci_write_config_byte(pdev, 0x85, c);
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printk(KERN_INFO"via686b fix: ISA bridge done\n");
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}
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static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
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{
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printk(KERN_INFO"via686b fix: IDE\n");
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/* Modify IDE controller setup */
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
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pci_write_config_byte(pdev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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pci_write_config_byte(pdev, 0x40, 0x0b);
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/* legacy mode */
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pci_write_config_byte(pdev, 0x42, 0x09);
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#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */
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/* disable read prefetch/write post buffers */
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pci_write_config_byte(pdev, 0x41, 0x02);
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/* use 3/4 as fifo thresh hold */
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pci_write_config_byte(pdev, 0x43, 0x0a);
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pci_write_config_byte(pdev, 0x44, 0x00);
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pci_write_config_byte(pdev, 0x45, 0x00);
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#else
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pci_write_config_byte(pdev, 0x41, 0xc2);
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pci_write_config_byte(pdev, 0x43, 0x35);
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pci_write_config_byte(pdev, 0x44, 0x1c);
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pci_write_config_byte(pdev, 0x45, 0x10);
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#endif
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printk(KERN_INFO"via686b fix: IDE done\n");
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}
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static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev)
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{
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/* irq routing */
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pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
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}
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static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev)
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{
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/* irq routing */
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pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
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}
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static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev)
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{
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unsigned int val;
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unsigned char c;
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/* enable IO */
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pci_write_config_byte(pdev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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pci_read_config_dword(pdev, 0x4, &val);
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pci_write_config_dword(pdev, 0x4, val | 1);
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/* route ac97 IRQ */
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pci_write_config_byte(pdev, 0x3c, 9);
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pci_read_config_byte(pdev, 0x8, &c);
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/* link control: enable link & SGD PCM output */
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pci_write_config_byte(pdev, 0x41, 0xcc);
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/* disable game port, FM, midi, sb, enable write to reg2c-2f */
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pci_write_config_byte(pdev, 0x42, 0x20);
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/* we are using Avance logic codec */
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pci_write_config_word(pdev, 0x2c, 0x1005);
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pci_write_config_word(pdev, 0x2e, 0x4710);
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pci_read_config_dword(pdev, 0x2c, &val);
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pci_write_config_byte(pdev, 0x42, 0x0);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
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loongson2e_686b_func0_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
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loongson2e_686b_func1_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2,
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loongson2e_686b_func2_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3,
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loongson2e_686b_func3_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,
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loongson2e_686b_func5_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
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loongson2e_nec_fixup);
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@@ -29,83 +29,60 @@
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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/*
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* PCI configuration cycle AD bus definition
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*/
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/* Type 0 */
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#define PCI_CFG_TYPE0_REG_SHF 0
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#define PCI_CFG_TYPE0_FUNC_SHF 8
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#ifdef CONFIG_LEMOTE_FULONG
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#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
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#define ID_SEL_BEGIN 11
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#else
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#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
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#define ID_SEL_BEGIN 10
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#endif
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#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
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/* Type 1 */
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#define PCI_CFG_TYPE1_REG_SHF 0
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#define PCI_CFG_TYPE1_FUNC_SHF 8
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#define PCI_CFG_TYPE1_DEV_SHF 11
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#define PCI_CFG_TYPE1_BUS_SHF 16
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static int bonito64_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus,
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unsigned int devfn, int where,
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u32 * data)
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{
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unsigned char busnum = bus->number;
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u32 busnum = bus->number;
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u32 addr, type;
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u32 dummy;
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u64 pci_addr;
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/* Algorithmics Bonito64 system controller. */
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if ((busnum == 0) && (PCI_SLOT(devfn) > 21)) {
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/* We number bus 0 devices from 0..21 */
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return -1;
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}
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/* Clear cause register bits */
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BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
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BONITO_PCICMD_MTABORT_CLR);
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/*
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* Setup pattern to be used as PCI "address" for
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* Type 0 cycle
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*/
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if (busnum == 0) {
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/* IDSEL */
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pci_addr = (u64) 1 << (PCI_SLOT(devfn) + 10);
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} else {
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/* Bus number */
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pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF;
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/* Device number */
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pci_addr |=
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PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF;
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}
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/* Function (same for Type 0/1) */
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pci_addr |= PCI_FUNC(devfn) << PCI_CFG_TYPE0_FUNC_SHF;
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/* Register number (same for Type 0/1) */
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pci_addr |= (where & ~0x3) << PCI_CFG_TYPE0_REG_SHF;
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void *addrp;
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int device = PCI_SLOT(devfn);
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int function = PCI_FUNC(devfn);
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int reg = where & ~3;
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if (busnum == 0) {
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/* Type 0 */
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BONITO_PCIMAP_CFG = pci_addr >> 16;
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/* Type 0 configuration for onboard PCI bus */
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if (device > MAX_DEV_NUM)
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return -1;
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addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
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type = 0;
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} else {
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/* Type 1 */
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BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000;
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/* Type 1 configuration for offboard PCI bus */
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addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
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type = 0x10000;
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}
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pci_addr &= 0xffff;
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/* Clear aborts */
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BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR;
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BONITO_PCIMAP_CFG = (addr >> 16) | type;
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/* Flush Bonito register block */
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dummy = BONITO_PCIMAP_CFG;
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iob(); /* sync */
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mmiowb();
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/* Perform access */
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addrp = CFG_SPACE_REG(addr & 0xffff);
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if (access_type == PCI_ACCESS_WRITE) {
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*(volatile u32 *) (_pcictrl_bonito_pcicfg + (u32)pci_addr) = *(u32 *) data;
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writel(cpu_to_le32(*data), addrp);
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#ifndef CONFIG_LEMOTE_FULONG
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/* Wait till done */
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while (BONITO_PCIMSTAT & 0xF);
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#endif
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} else {
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*(u32 *) data = *(volatile u32 *) (_pcictrl_bonito_pcicfg + (u32)pci_addr);
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*data = le32_to_cpu(readl(addrp));
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}
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/* Detect Master/Target abort */
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@@ -121,6 +98,7 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
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}
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return 0;
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}
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