Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King: - clang assembly fixes from Ard - optimisations and cleanups for Aurora L2 cache support - efficient L2 cache support for secure monitor API on Exynos SoCs - debug menu cleanup from Daniel Thompson to allow better behaviour for multiplatform kernels - StrongARM SA11x0 conversion to irq domains, and pxa_timer - kprobes updates for older ARM CPUs - move probes support out of arch/arm/kernel to arch/arm/probes - add inline asm support for the rbit (reverse bits) instruction - provide an ARM mode secondary CPU entry point (for Qualcomm CPUs) - remove the unused ARMv3 user access code - add driver_override support to AMBA Primecell bus * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (55 commits) ARM: 8256/1: driver coamba: add device binding path 'driver_override' ARM: 8301/1: qcom: Use secondary_startup_arm() ARM: 8302/1: Add a secondary_startup that assumes ARM mode ARM: 8300/1: teach __asmeq that r11 == fp and r12 == ip ARM: kprobes: Fix compilation error caused by superfluous '*' ARM: 8297/1: cache-l2x0: optimize aurora range operations ARM: 8296/1: cache-l2x0: clean up aurora cache handling ARM: 8284/1: sa1100: clear RCSR_SMR on resume ARM: 8283/1: sa1100: collie: clear PWER register on machine init ARM: 8282/1: sa1100: use handle_domain_irq ARM: 8281/1: sa1100: move GPIO-related IRQ code to gpio driver ARM: 8280/1: sa1100: switch to irq_domain_add_simple() ARM: 8279/1: sa1100: merge both GPIO irqdomains ARM: 8278/1: sa1100: split irq handling for low GPIOs ARM: 8291/1: replace magic number with PAGE_SHIFT macro in fixup_pv code ARM: 8290/1: decompressor: fix a wrong comment ARM: 8286/1: mm: Fix dma_contiguous_reserve comment ARM: 8248/1: pm: remove outdated comment ARM: 8274/1: Fix DEBUG_LL for multi-platform kernels (without PL01X) ARM: 8273/1: Seperate DEBUG_UART_PHYS from DEBUG_LL on EP93XX ...
このコミットが含まれているのは:
Linus Torvalds
@@ -11,6 +11,7 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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@@ -50,7 +51,7 @@ static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int
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static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return offset < 11 ? (IRQ_GPIO0 + offset) : (IRQ_GPIO11 - 11 + offset);
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return IRQ_GPIO0 + offset;
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}
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static struct gpio_chip sa1100_gpio_chip = {
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@@ -64,7 +65,203 @@ static struct gpio_chip sa1100_gpio_chip = {
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.ngpio = GPIO_MAX + 1,
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};
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/*
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* SA1100 GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* Use this instead of directly setting GRER/GFER.
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*/
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static int GPIO_IRQ_rising_edge;
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static int GPIO_IRQ_falling_edge;
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static int GPIO_IRQ_mask;
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static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
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{
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unsigned int mask;
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mask = BIT(d->hwirq);
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if (type == IRQ_TYPE_PROBE) {
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if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
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return 0;
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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if (type & IRQ_TYPE_EDGE_RISING)
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GPIO_IRQ_rising_edge |= mask;
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else
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GPIO_IRQ_rising_edge &= ~mask;
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if (type & IRQ_TYPE_EDGE_FALLING)
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GPIO_IRQ_falling_edge |= mask;
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else
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GPIO_IRQ_falling_edge &= ~mask;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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return 0;
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}
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/*
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* GPIO IRQs must be acknowledged.
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*/
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static void sa1100_gpio_ack(struct irq_data *d)
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{
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GEDR = BIT(d->hwirq);
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}
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static void sa1100_gpio_mask(struct irq_data *d)
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{
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unsigned int mask = BIT(d->hwirq);
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GPIO_IRQ_mask &= ~mask;
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GRER &= ~mask;
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GFER &= ~mask;
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}
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static void sa1100_gpio_unmask(struct irq_data *d)
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{
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unsigned int mask = BIT(d->hwirq);
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GPIO_IRQ_mask |= mask;
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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}
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static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
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{
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if (on)
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PWER |= BIT(d->hwirq);
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else
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PWER &= ~BIT(d->hwirq);
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return 0;
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}
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/*
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* This is for GPIO IRQs
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*/
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static struct irq_chip sa1100_gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = sa1100_gpio_ack,
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.irq_mask = sa1100_gpio_mask,
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.irq_unmask = sa1100_gpio_unmask,
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.irq_set_type = sa1100_gpio_type,
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.irq_set_wake = sa1100_gpio_wake,
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};
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static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip,
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handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
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.map = sa1100_gpio_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static struct irq_domain *sa1100_gpio_irqdomain;
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/*
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* IRQ 0-11 (GPIO) handler. We enter here with the
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* irq_controller_lock held, and IRQs disabled. Decode the IRQ
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* and call the handler.
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*/
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static void
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sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int mask;
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mask = GEDR;
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do {
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/*
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* clear down all currently active IRQ sources.
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* We will be processing them all.
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*/
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GEDR = mask;
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irq = IRQ_GPIO0;
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do {
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if (mask & 1)
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generic_handle_irq(irq);
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mask >>= 1;
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irq++;
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} while (mask);
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mask = GEDR;
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} while (mask);
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}
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static int sa1100_gpio_suspend(void)
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{
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/*
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* Set the appropriate edges for wakeup.
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*/
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GRER = PWER & GPIO_IRQ_rising_edge;
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GFER = PWER & GPIO_IRQ_falling_edge;
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/*
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* Clear any pending GPIO interrupts.
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*/
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GEDR = GEDR;
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return 0;
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}
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static void sa1100_gpio_resume(void)
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{
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GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
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GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
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}
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static struct syscore_ops sa1100_gpio_syscore_ops = {
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.suspend = sa1100_gpio_suspend,
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.resume = sa1100_gpio_resume,
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};
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static int __init sa1100_gpio_init_devicefs(void)
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{
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register_syscore_ops(&sa1100_gpio_syscore_ops);
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return 0;
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}
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device_initcall(sa1100_gpio_init_devicefs);
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void __init sa1100_init_gpio(void)
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{
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/* clear all GPIO edge detects */
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GFER = 0;
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GRER = 0;
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GEDR = -1;
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gpiochip_add(&sa1100_gpio_chip);
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sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
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28, IRQ_GPIO0,
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&sa1100_gpio_irqdomain_ops, NULL);
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/*
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* Install handlers for GPIO 0-10 edge detect interrupts
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*/
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irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
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irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
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/*
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* Install handler for GPIO 11-27 edge detect interrupts
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*/
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irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
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}
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