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[PATCH] mips: nuke trailing whitespace

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Ralf Baechle
2005-09-03 15:56:17 -07:00
committed by Linus Torvalds
parent 875d43e72b
commit 42a3b4f25a
137 changed files with 596 additions and 596 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/asm-mips/asmmacro.h
View File

@@ -7,10 +7,10 @@
*/
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H
#include <linux/config.h>
#include <asm/hazards.h>
#ifdef CONFIG_32BIT
#include <asm/asmmacro-32.h>
#endif

4
include/asm-mips/bitops.h
View File

@@ -20,13 +20,13 @@
#define SZLONG_MASK 31UL
#define __LL "ll "
#define __SC "sc "
#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
#elif (_MIPS_SZLONG == 64)
#define SZLONG_LOG 6
#define SZLONG_MASK 63UL
#define __LL "lld "
#define __SC "scd "
#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
#endif
#ifdef __KERNEL__

6
include/asm-mips/ddb5xxx/ddb5477.h
View File

@@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
* All PCI irq but INTC are active low.
*/
/*
/*
* irq number block assignment
*/
@@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
@@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */

4
include/asm-mips/fpregdef.h
View File

@@ -13,7 +13,7 @@
#define _ASM_FPREGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
@@ -56,7 +56,7 @@
#define fcr31 $31 /* FPU status register */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define fv0 $f0 /* return value */

8
include/asm-mips/fpu.h
View File

@@ -82,7 +82,7 @@ do { \
static inline int is_fpu_owner(void)
{
return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
}
static inline void own_fpu(void)
@@ -90,7 +90,7 @@ static inline void own_fpu(void)
if (cpu_has_fpu) {
__enable_fpu();
KSTK_STATUS(current) |= ST0_CU1;
set_thread_flag(TIF_USEDFPU);
set_thread_flag(TIF_USEDFPU);
}
}
@@ -98,7 +98,7 @@ static inline void lose_fpu(void)
{
if (cpu_has_fpu) {
KSTK_STATUS(current) &= ~ST0_CU1;
clear_thread_flag(TIF_USEDFPU);
clear_thread_flag(TIF_USEDFPU);
__disable_fpu();
}
}
@@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk)
static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
{
if (cpu_has_fpu) {
if ((tsk == current) && is_fpu_owner())
if ((tsk == current) && is_fpu_owner())
_save_fp(current);
return tsk->thread.fpu.hard.fpr;
}

8
include/asm-mips/ip32/mace.h
View File

@@ -94,7 +94,7 @@ struct mace_video {
unsigned long xxx; /* later... */
};
/*
/*
* Ethernet interface
*/
struct mace_ethernet {
@@ -129,7 +129,7 @@ struct mace_ethernet {
volatile unsigned long rx_fifo;
};
/*
/*
* Peripherals
*/
@@ -251,7 +251,7 @@ struct mace_timers {
timer_reg audio_out2;
timer_reg video_in1;
timer_reg video_in2;
timer_reg video_out;
timer_reg video_out;
};
struct mace_perif {
@@ -272,7 +272,7 @@ struct mace_perif {
};
/*
/*
* ISA peripherals
*/

4
include/asm-mips/lasat/serial.h
View File

@@ -1,13 +1,13 @@
#include <asm/lasat/lasat.h>
/* Lasat 100 boards serial configuration */
#define LASAT_BASE_BAUD_100 ( 7372800 / 16 )
#define LASAT_BASE_BAUD_100 ( 7372800 / 16 )
#define LASAT_UART_REGS_BASE_100 0x1c8b0000
#define LASAT_UART_REGS_SHIFT_100 2
#define LASATINT_UART_100 8
/* * LASAT 200 boards serial configuration */
#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
#define LASAT_UART_REGS_SHIFT_200 3
#define LASATINT_UART_200 13

2
include/asm-mips/mach-au1x00/au1000.h
View File

@@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
#define PCI_IO_START 0
#define PCI_IO_END 0
#define PCI_MEM_START 0
#define PCI_MEM_END 0
#define PCI_MEM_END 0
#define PCI_FIRST_DEVFN 0
#define PCI_LAST_DEVFN 0
#endif

2
include/asm-mips/mach-db1x00/db1x00.h
View File

@@ -23,7 +23,7 @@
*
* ########################################################################
*
*
*
*/
#ifndef __ASM_DB1X00_H
#define __ASM_DB1X00_H

2
include/asm-mips/mach-jazz/floppy.h
View File

@@ -92,7 +92,7 @@ static inline int fd_request_irq(void)
return request_irq(FLOPPY_IRQ, floppy_interrupt,
SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
}
static inline void fd_free_irq(void)
{
free_irq(FLOPPY_IRQ, NULL);

4
include/asm-mips/mach-pb1x00/pb1500.h
View File

@@ -33,11 +33,11 @@
#define PCI_BOARD_REG 0xAE000010
#define PCMCIA_BOARD_REG 0xAE000010
#define PC_DEASSERT_RST 0x80
#define PC_DRV_EN 0x10
#define PC_DRV_EN 0x10
#define PB1500_G_CONTROL 0xAE000014
#define PB1500_RST_VDDI 0xAE00001C
#define PB1500_LEDS 0xAE000018
#define PB1500_HEX_LED 0xAF000004
#define PB1500_HEX_LED_BLANK 0xAF000008

68
include/asm-mips/r4kcache.h
View File

@@ -171,11 +171,11 @@ static inline void blast_dcache16(void)
unsigned long start = INDEX_BASE;
unsigned long end = start + current_cpu_data.dcache.waysize;
unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
unsigned long ws_end = current_cpu_data.dcache.ways <<
unsigned long ws_end = current_cpu_data.dcache.ways <<
current_cpu_data.dcache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
}
@@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page)
current_cpu_data.dcache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
}
@@ -214,8 +214,8 @@ static inline void blast_icache16(void)
current_cpu_data.icache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr|ws,Index_Invalidate_I);
}
@@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page)
current_cpu_data.icache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr|ws,Index_Invalidate_I);
}
@@ -249,11 +249,11 @@ static inline void blast_scache16(void)
unsigned long start = INDEX_BASE;
unsigned long end = start + current_cpu_data.scache.waysize;
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
unsigned long ws_end = current_cpu_data.scache.ways <<
unsigned long ws_end = current_cpu_data.scache.ways <<
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page)
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x200)
cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -318,8 +318,8 @@ static inline void blast_dcache32(void)
current_cpu_data.dcache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
}
@@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page)
current_cpu_data.dcache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
}
@@ -357,8 +357,8 @@ static inline void blast_icache32(void)
current_cpu_data.icache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
cache32_unroll32(addr|ws,Index_Invalidate_I);
}
@@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page)
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
for (addr = start; addr < end; addr += 0x400)
cache32_unroll32(addr|ws,Index_Invalidate_I);
}
@@ -392,11 +392,11 @@ static inline void blast_scache32(void)
unsigned long start = INDEX_BASE;
unsigned long end = start + current_cpu_data.scache.waysize;
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
unsigned long ws_end = current_cpu_data.scache.ways <<
unsigned long ws_end = current_cpu_data.scache.ways <<
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page)
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400)
cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -461,8 +461,8 @@ static inline void blast_icache64(void)
current_cpu_data.icache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x800)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x800)
cache64_unroll32(addr|ws,Index_Invalidate_I);
}
@@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page)
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x800)
for (addr = start; addr < end; addr += 0x800)
cache64_unroll32(addr|ws,Index_Invalidate_I);
}
@@ -496,11 +496,11 @@ static inline void blast_scache64(void)
unsigned long start = INDEX_BASE;
unsigned long end = start + current_cpu_data.scache.waysize;
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
unsigned long ws_end = current_cpu_data.scache.ways <<
unsigned long ws_end = current_cpu_data.scache.ways <<
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x800)
cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page)
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x800)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x800)
cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -561,11 +561,11 @@ static inline void blast_scache128(void)
unsigned long start = INDEX_BASE;
unsigned long end = start + current_cpu_data.scache.waysize;
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
unsigned long ws_end = current_cpu_data.scache.ways <<
unsigned long ws_end = current_cpu_data.scache.ways <<
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x1000)
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
}
@@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page)
current_cpu_data.scache.waybit;
unsigned long ws, addr;
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x1000)
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x1000)
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
}

2
include/asm-mips/rtc.h
View File

@@ -1,5 +1,5 @@
/*
* include/asm-mips/rtc.h
* include/asm-mips/rtc.h
*
* (Really an interface for drivers/char/genrtc.c)
*

2
include/asm-mips/sgi/gio.h
View File

@@ -16,7 +16,7 @@
*
* The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
* three physical connectors, but only two slots, GFX and EXP0.
*
*
* There is 10MB of GIO address space for GIO64 slot devices
* slot# slot type address range size
* ----- --------- ----------------------- -----

4
include/asm-mips/sgi/hpc3.h
View File

@@ -221,7 +221,7 @@ struct hpc3_regs {
#define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */
u32 _unused1[0x14000/4 - 5]; /* padding */
/* Now direct PIO per-HPC3 peripheral access to external regs. */
volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
u32 _unused2[0x7c00/4];
@@ -304,7 +304,7 @@ struct hpc3_regs {
volatile u32 bbram[8192-50-14]; /* Battery backed ram */
};
/*
/*
* It is possible to have two HPC3's within the address space on
* one machine, though only having one is more likely on an Indy.
*/

4
include/asm-mips/sgi/ioc.h
View File

@@ -16,7 +16,7 @@
#include <linux/types.h>
#include <asm/sgi/pi1.h>
/*
/*
* All registers are 8-bit wide alligned on 32-bit boundary. Bad things
* happen if you try word access them. You have been warned.
*/
@@ -138,7 +138,7 @@ struct sgioc_regs {
u8 _sysid[3];
volatile u8 sysid;
#define SGIOC_SYSID_FULLHOUSE 0x01
#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1)
u32 _unused2;
u8 _read[3];

2
include/asm-mips/sgi/ip22.h
View File

@@ -12,7 +12,7 @@
#ifndef _SGI_IP22_H
#define _SGI_IP22_H
/*
/*
* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups

6
include/asm-mips/sgi/mc.h
View File

@@ -182,14 +182,14 @@ struct sgimc_regs {
volatile u32 dtlb_hi3;
u32 _unused33;
volatile u32 dtlb_lo3;
u32 _unused34[0x0392];
u32 _unused35;
volatile u32 rpsscounter; /* Chirps at 100ns */
u32 _unused36[0x1000/4-2*4];
u32 _unused37;
volatile u32 maddronly; /* Address DMA goes at */
u32 _unused38;

12
include/asm-mips/sibyte/carmel.h
View File

@@ -25,12 +25,12 @@
#define SIBYTE_BOARD_NAME "Carmel"
#define GPIO_PHY_INTERRUPT 2
#define GPIO_NONMASKABLE_INT 3
#define GPIO_CF_INSERTED 6
#define GPIO_MONTEREY_RESET 7
#define GPIO_QUADUART_INT 8
#define GPIO_CF_INT 9
#define GPIO_PHY_INTERRUPT 2
#define GPIO_NONMASKABLE_INT 3
#define GPIO_CF_INSERTED 6
#define GPIO_MONTEREY_RESET 7
#define GPIO_QUADUART_INT 8
#define GPIO_CF_INT 9
#define GPIO_FPGA_CCLK 10
#define GPIO_FPGA_DOUT 11
#define GPIO_FPGA_DIN 12

38
include/asm-mips/sibyte/sb1250_defs.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* Global constants and macros File: sb1250_defs.h
*
*
* Global constants and macros File: sb1250_defs.h
*
* This file contains macros and definitions used by the other
* include files.
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -105,7 +105,7 @@
#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00
#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100
/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
#define SIBYTE_HDR_FMASK(chip, pass) \
(SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
@@ -150,31 +150,31 @@
/* *********************************************************************
* Naming schemes for constants in these files:
*
* M_xxx MASK constant (identifies bits in a register).
*
* M_xxx MASK constant (identifies bits in a register).
* For multi-bit fields, all bits in the field will
* be set.
*
* K_xxx "Code" constant (value for data in a multi-bit
* field). The value is right justified.
*
* V_xxx "Value" constant. This is the same as the
* V_xxx "Value" constant. This is the same as the
* corresponding "K_xxx" constant, except it is
* shifted to the correct position in the register.
*
* S_xxx SHIFT constant. This is the number of bits that
* a field value (code) needs to be shifted
* a field value (code) needs to be shifted
* (towards the left) to put the value in the right
* position for the register.
*
* A_xxx ADDRESS constant. This will be a physical
* A_xxx ADDRESS constant. This will be a physical
* address. Use the PHYS_TO_K1 macro to generate
* a K1SEG address.
*
* R_xxx RELATIVE offset constant. This is an offset from
* an A_xxx constant (usually the first register in
* a group).
*
*
* G_xxx(X) GET value. This macro obtains a multi-bit field
* from a register, masks it, and shifts it to
* the bottom of the register (retrieving a K_xxx
@@ -189,7 +189,7 @@
/*
* Cast to 64-bit number. Presumably the syntax is different in
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
*
* Note: you'll need to define uint32_t and uint64_t in your headers.

42
include/asm-mips/sibyte/sb1250_dma.h
View File

@@ -1,24 +1,24 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* DMA definitions File: sb1250_dma.h
*
*
* This module contains constants and macros useful for
* programming the SB1250's DMA controllers, both the data mover
* and the Ethernet DMA.
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -28,7 +28,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -43,9 +43,9 @@
* DMA Registers
********************************************************************* */
/*
/*
* Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
* Registers: DMA_CONFIG0_MAC_x_RX_CH_0
* Registers: DMA_CONFIG0_MAC_x_RX_CH_0
* Registers: DMA_CONFIG0_MAC_x_TX_CH_0
* Registers: DMA_CONFIG0_SER_x_RX
* Registers: DMA_CONFIG0_SER_x_TX
@@ -98,7 +98,7 @@
/*
* Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_DMA_x_TX_CH_0
* Registers: DMA_CONFIG1_SER_x_RX
* Registers: DMA_CONFIG1_SER_x_TX
@@ -152,11 +152,11 @@
/*
* DMA Descriptor Count Registers (Table 7-8)
*/
/* No bitfields */
/*
/*
* Current Descriptor Address Register (Table 7-11)
*/
@@ -275,14 +275,14 @@
#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
/*
/*
* Ethernet Descriptor Status Bits (Table 7-15)
*/
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/* Note: BADTCPCS is actually in DSCR_B options field */
#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
#endif /* 1250 PASS2 || 112x PASS1 */
@@ -324,7 +324,7 @@
#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
/*
/*
* Ethernet Transmit Options (Table 7-17)
*/
@@ -377,7 +377,7 @@
* Data Mover Registers
********************************************************************* */
/*
/*
* Data Mover Descriptor Base Address Register (Table 7-22)
* Register: DM_DSCR_BASE_0
* Register: DM_DSCR_BASE_1
@@ -414,7 +414,7 @@
#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
/*
/*
* Data Mover Descriptor Count Register (Table 7-25)
*/

24
include/asm-mips/sibyte/sb1250_genbus.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* Generic Bus Constants File: sb1250_genbus.h
*
* This module contains constants and macros useful for
*
* This module contains constants and macros useful for
* manipulating the SB1250's Generic Bus interface
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */

24
include/asm-mips/sibyte/sb1250_int.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* Interrupt Mapper definitions File: sb1250_int.h
*
*
* This module contains constants for manipulating the SB1250's
* interrupt mapper and definitions for the interrupt sources.
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -43,7 +43,7 @@
/*
* Interrupt sources (Table 4-8, UM 0.2)
*
*
* First, the interrupt numbers.
*/

22
include/asm-mips/sibyte/sb1250_l2c.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* L2 Cache constants and macros File: sb1250_l2c.h
*
*
* This module contains constants useful for manipulating the
* level 2 cache.
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */

32
include/asm-mips/sibyte/sb1250_ldt.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* LDT constants File: sb1250_ldt.h
*
* This module contains constants and macros to describe
* the LDT interface on the SB1250.
*
*
* This module contains constants and macros to describe
* the LDT interface on the SB1250.
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -155,7 +155,7 @@
/*
* LDT Status Register (Table 8-14). Note that these constants
* assume you've read the command and status register
* assume you've read the command and status register
* together (32-bit read at offset 0x04)
*
* These bits also apply to the secondary status
@@ -183,8 +183,8 @@
#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
/*
* Bridge Control Register (Table 8-16). Note that these
* constants assume you've read the register as a 32-bit
* Bridge Control Register (Table 8-16). Note that these
* constants assume you've read the register as a 32-bit
* read (offset 0x3C)
*/

26
include/asm-mips/sibyte/sb1250_mac.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* MAC constants and macros File: sb1250_mac.h
*
*
* This module contains constants and macros for the SB1250's
* ethernet controllers.
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -311,7 +311,7 @@
/*
* These constants are used to configure the fields within the Frame
* Configuration Register.
* Configuration Register.
*/
#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */
@@ -393,7 +393,7 @@
* Register: MAC_INT_MASK_2
*/
/*
/*
* Use these constants to shift the appropriate channel
* into the CH0 position so the same tests can be used
* on each channel.

28
include/asm-mips/sibyte/sb1250_mc.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* Memory Controller constants File: sb1250_mc.h
*
*
* Memory Controller constants File: sb1250_mc.h
*
* This module contains constants and macros useful for
* programming the memory controller.
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -166,7 +166,7 @@
#define K_MC_REF_RATE_100MHz 0x62
#define K_MC_REF_RATE_133MHz 0x81
#define K_MC_REF_RATE_200MHz 0xC4
#define K_MC_REF_RATE_200MHz 0xC4
#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
@@ -228,7 +228,7 @@
V_MC_ADDR_DRIVE_DEFAULT | \
V_MC_DATA_DRIVE_DEFAULT | \
V_MC_CLOCK_DRIVE_DEFAULT | \
V_MC_REF_RATE_DEFAULT
V_MC_REF_RATE_DEFAULT

68
include/asm-mips/sibyte/sb1250_regs.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* Register Definitions File: sb1250_regs.h
*
*
* This module contains the addresses of the on-chip peripherals
* on the SB1250.
*
*
* SB1250 specification level: 01/02/2002
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -40,20 +40,20 @@
/* *********************************************************************
* Some general notes:
*
*
* For the most part, when there is more than one peripheral
* of the same type on the SOC, the constants below will be
* offsets from the base of each peripheral. For example,
* the MAC registers are described as offsets from the first
* MAC register, and there will be a MAC_REGISTER() macro
* to calculate the base address of a given MAC.
*
* to calculate the base address of a given MAC.
*
* The information in this file is based on the SB1250 SOC
* manual version 0.2, July 2000.
********************************************************************* */
/* *********************************************************************
/* *********************************************************************
* Memory Controller Registers
********************************************************************* */
@@ -101,7 +101,7 @@
#define R_MC_TEST_ECC 0x0000000420
#define R_MC_MCLK_CFG 0x0000000500
/* *********************************************************************
/* *********************************************************************
* L2 Cache Control Registers
********************************************************************* */
@@ -126,7 +126,7 @@
#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
/* *********************************************************************
/* *********************************************************************
* PCI Interface Registers
********************************************************************* */
@@ -134,7 +134,7 @@
#define A_PCI_TYPE01_HEADER 0x00DE000800
/* *********************************************************************
/* *********************************************************************
* Ethernet DMA and MACs
********************************************************************* */
@@ -184,7 +184,7 @@
(R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \
(reg))
/*
/*
* DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
*/
@@ -259,7 +259,7 @@
#define MAC_CHMAP_COUNT 4
/* *********************************************************************
/* *********************************************************************
* DUART Registers
********************************************************************* */
@@ -363,7 +363,7 @@
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
/* *********************************************************************
* Synchronous Serial Registers
********************************************************************* */
@@ -397,7 +397,7 @@
(reg))
/*
/*
* DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
*/
@@ -457,7 +457,7 @@
#define R_SER_RMON_RX_ERRORS 0x000001F0
#define R_SER_RMON_RX_BADADDR 0x000001F8
/* *********************************************************************
/* *********************************************************************
* Generic Bus Registers
********************************************************************* */
@@ -513,7 +513,7 @@
#define R_IO_PCMCIA_CFG 0x0A60
#define R_IO_PCMCIA_STATUS 0x0A70
/* *********************************************************************
/* *********************************************************************
* GPIO Registers
********************************************************************* */
@@ -537,7 +537,7 @@
#define R_GPIO_PIN_CLR 0x30
#define R_GPIO_PIN_SET 0x38
/* *********************************************************************
/* *********************************************************************
* SMBus Registers
********************************************************************* */
@@ -573,7 +573,7 @@
#define R_SMB_CONTROL 0x0000000060
#define R_SMB_PEC 0x0000000070
/* *********************************************************************
/* *********************************************************************
* Timer Registers
********************************************************************* */
@@ -641,7 +641,7 @@
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
/* *********************************************************************
* System Control Registers
********************************************************************* */
@@ -649,7 +649,7 @@
#define A_SCD_SYSTEM_CFG 0x0010020008
#define A_SCD_SYSTEM_MANUF 0x0010038000
/* *********************************************************************
/* *********************************************************************
* System Address Trap Registers
********************************************************************* */
@@ -672,7 +672,7 @@
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
/* *********************************************************************
* System Interrupt Mapper Registers
********************************************************************* */
@@ -701,7 +701,7 @@
#define R_IMR_INTERRUPT_MAP_BASE 0x0200
#define R_IMR_INTERRUPT_MAP_COUNT 64
/* *********************************************************************
/* *********************************************************************
* System Performance Counter Registers
********************************************************************* */
@@ -711,7 +711,7 @@
#define A_SCD_PERF_CNT_2 0x00100204E0
#define A_SCD_PERF_CNT_3 0x00100204E8
/* *********************************************************************
/* *********************************************************************
* System Bus Watcher Registers
********************************************************************* */
@@ -726,13 +726,13 @@
#define A_BUS_L2_ERRORS 0x00100208C0
#define A_BUS_MEM_IO_ERRORS 0x00100208C8
/* *********************************************************************
/* *********************************************************************
* System Debug Controller Registers
********************************************************************* */
#define A_SCD_JTAG_BASE 0x0010000000
/* *********************************************************************
/* *********************************************************************
* System Trace Buffer Registers
********************************************************************* */
@@ -755,7 +755,7 @@
#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
/* *********************************************************************
/* *********************************************************************
* System Generic DMA Registers
********************************************************************* */

36
include/asm-mips/sibyte/sb1250_scd.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* SCD Constants and Macros File: sb1250_scd.h
*
*
* This module contains constants and macros useful for
* manipulating the System Control and Debug module on the 1250.
*
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -130,40 +130,40 @@
/* System Manufacturing Register
* Register: SCD_SYSTEM_MANUF
*/
/* Wafer ID: bits 31:0 */
#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
#define S_SYS_BIN _SB_MAKE64(32)
#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)
#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN)
#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
/* Wafer ID: bits 39:36 */
#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
/* Wafer ID: bits 39:0 */
#define S_SYS_WAFERID_300 _SB_MAKE64(0)
#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300)
#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
#define S_SYS_XPOS _SB_MAKE64(40)
#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS)
#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS)
#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
#define S_SYS_YPOS _SB_MAKE64(46)
#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)
#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)
#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
/*
* System Config Register (Table 4-2)
* Register: SCD_SYSTEM_CFG

24
include/asm-mips/sibyte/sb1250_smbus.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* SMBUS Constants File: sb1250_smbus.h
*
* This module contains constants and macros useful for
*
* This module contains constants and macros useful for
* manipulating the SB1250's SMbus devices.
*
*
* SB1250 specification level: 01/02/2002
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */

12
include/asm-mips/sibyte/sb1250_syncser.h
View File

@@ -7,17 +7,17 @@
* manipulating the SB1250's Synchronous Serial
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */

30
include/asm-mips/sibyte/sb1250_uart.h
View File

@@ -1,23 +1,23 @@
/* *********************************************************************
* SB1250 Board Support Package
*
*
* UART Constants File: sb1250_uart.h
*
* This module contains constants and macros useful for
*
* This module contains constants and macros useful for
* manipulating the SB1250's UARTs
*
* SB1250 specification level: User's manual 1/02/02
*
*
* Author: Mitch Lichtenberg
*
*********************************************************************
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
@@ -37,7 +37,7 @@
#include "sb1250_defs.h"
/* **********************************************************************
/* **********************************************************************
* DUART Registers
********************************************************************** */
@@ -145,7 +145,7 @@
#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
/*
* DUART Status Register (Table 10-6)
@@ -165,7 +165,7 @@
/*
* DUART Baud Rate Register (Table 10-7)
* Register: DUART_CLK_SEL_A
* Register: DUART_CLK_SEL_A
* Register: DUART_CLK_SEL_B
*/
@@ -332,7 +332,7 @@
(chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
/*
* Full Interrupt Control Register
*/

4
include/asm-mips/sigcontext.h
View File

@@ -10,7 +10,7 @@
#define _ASM_SIGCONTEXT_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
@@ -38,7 +38,7 @@ struct sigcontext {
};
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
/*

2
include/asm-mips/socket.h
View File

@@ -82,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
* @SOCK_STREAM - stream (connection) socket
* @SOCK_RAW - raw socket
* @SOCK_RDM - reliably-delivered message
* @SOCK_SEQPACKET - sequential packet socket
* @SOCK_SEQPACKET - sequential packet socket
* @SOCK_PACKET - linux specific way of getting packets at the dev level.
* For writing rarp and other similar things on the user level.
*/

2
include/asm-mips/statfs.h
View File

@@ -57,7 +57,7 @@ struct statfs64 {
};
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64
struct statfs64 { /* Same as struct statfs */

2
include/asm-mips/titan_dep.h
View File

@@ -228,4 +228,4 @@ extern unsigned long ocd_base;
#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
#endif
#endif

52
include/asm-mips/tx4927/tx4927.h
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@@ -45,14 +45,14 @@
/* TX4927 SDRAM controller (64-bit registers) */
#define TX4927_SDRAMC_BASE 0x8000
#define TX4927_SDRAMC_SDCCR0 0x8000
#define TX4927_SDRAMC_BASE 0x8000
#define TX4927_SDRAMC_SDCCR0 0x8000
#define TX4927_SDRAMC_SDCCR1 0x8008
#define TX4927_SDRAMC_SDCCR2 0x8010
#define TX4927_SDRAMC_SDCCR3 0x8018
#define TX4927_SDRAMC_SDCTR 0x8040
#define TX4927_SDRAMC_SDCMD 0x8058
#define TX4927_SDRAMC_LIMIT 0x8fff
#define TX4927_SDRAMC_LIMIT 0x8fff
/* TX4927 external bus controller (64-bit registers) */
@@ -289,8 +289,8 @@
/* TX4927 serial port 0 (32-bit registers) */
#define TX4927_SIO0_BASE 0xf300
#define TX4927_SIO0_SILCR0 0xf300
#define TX4927_SIO0_BASE 0xf300
#define TX4927_SIO0_SILCR0 0xf300
#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SILCR0_RWUB BM_15_15
#define TX4927_SIO0_SILCR0_TWUB BM_14_14
@@ -309,7 +309,7 @@
#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)
#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01
#define TX4927_SIO0_SIDICR0 0xf304
#define TX4927_SIO0_SIDICR0 0xf304
#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SIDICR0_TDE BM_15_15
#define TX4927_SIO0_SIDICR0_RDE BM_14_14
@@ -330,7 +330,7 @@
#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02
#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01
#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00
#define TX4927_SIO0_SIDISR0 0xf308
#define TX4927_SIO0_SIDISR0 0xf308
#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SIDISR0_UBRK BM_15_15
#define TX4927_SIO0_SIDISR0_UVALID BM_14_14
@@ -344,7 +344,7 @@
#define TX4927_SIO0_SIDISR0_STIS BM_06_06
#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05
#define TX4927_SIO0_SIDISR0_RFDN BM_00_04
#define TX4927_SIO0_SISCISR0 0xf30c
#define TX4927_SIO0_SISCISR0 0xf30c
#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31
#define TX4927_SIO0_SISCISR0_OERS BM_05_05
#define TX4927_SIO0_SISCISR0_CTSS BM_04_04
@@ -352,7 +352,7 @@
#define TX4927_SIO0_SISCISR0_TRDY BM_02_02
#define TX4927_SIO0_SISCISR0_TXALS BM_01_01
#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00
#define TX4927_SIO0_SIFCR0 0xf310
#define TX4927_SIO0_SIFCR0 0xf310
#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SIFCR0_SWRST BM_16_31
#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14
@@ -370,7 +370,7 @@
#define TX4927_SIO0_SIFCR0_TFRST BM_02_02
#define TX4927_SIO0_SIFCR0_RFRST BM_01_01
#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00
#define TX4927_SIO0_SIFLCR0 0xf314
#define TX4927_SIO0_SIFLCR0 0xf314
#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31
#define TX4927_SIO0_SIFLCR0_RCS BM_12_12
#define TX4927_SIO0_SIFLCR0_TES BM_11_11
@@ -381,7 +381,7 @@
#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06
#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04
#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00
#define TX4927_SIO0_SIBGR0 0xf318
#define TX4927_SIO0_SIBGR0 0xf318
#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31
#define TX4927_SIO0_SIBGR0_BCLK BM_08_09
#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)
@@ -389,28 +389,28 @@
#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09
#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09
#define TX4927_SIO0_SIBGR0_BRD BM_00_07
#define TX4927_SIO0_SITFIF00 0xf31c
#define TX4927_SIO0_SITFIF00 0xf31c
#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31
#define TX4927_SIO0_SITFIF00_TXD BM_00_07
#define TX4927_SIO0_SIRFIFO0 0xf320
#define TX4927_SIO0_SIRFIFO0 0xf320
#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31
#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07
#define TX4927_SIO0_SIRFIFO0 0xf320
#define TX4927_SIO0_LIMIT 0xf3ff
#define TX4927_SIO0_SIRFIFO0 0xf320
#define TX4927_SIO0_LIMIT 0xf3ff
/* TX4927 serial port 1 (32-bit registers) */
#define TX4927_SIO1_BASE 0xf400
#define TX4927_SIO1_SILCR1 0xf400
#define TX4927_SIO1_SIDICR1 0xf404
#define TX4927_SIO1_SIDISR1 0xf408
#define TX4927_SIO1_SISCISR1 0xf40c
#define TX4927_SIO1_SIFCR1 0xf410
#define TX4927_SIO1_SIFLCR1 0xf414
#define TX4927_SIO1_SIBGR1 0xf418
#define TX4927_SIO1_SITFIF01 0xf41c
#define TX4927_SIO1_SIRFIFO1 0xf420
#define TX4927_SIO1_LIMIT 0xf4ff
#define TX4927_SIO1_BASE 0xf400
#define TX4927_SIO1_SILCR1 0xf400
#define TX4927_SIO1_SIDICR1 0xf404
#define TX4927_SIO1_SIDISR1 0xf408
#define TX4927_SIO1_SISCISR1 0xf40c
#define TX4927_SIO1_SIFCR1 0xf410
#define TX4927_SIO1_SIFLCR1 0xf414
#define TX4927_SIO1_SIBGR1 0xf418
#define TX4927_SIO1_SITFIF01 0xf41c
#define TX4927_SIO1_SIRFIFO1 0xf420
#define TX4927_SIO1_LIMIT 0xf4ff
/* TX4927 parallel port (32-bit registers) */

4
include/asm-mips/tx4927/tx4927_pci.h
View File

@@ -5,8 +5,8 @@
*
* Copyright (C) 2000-2001 Toshiba Corporation
*/
#ifndef __ASM_TX4927_TX4927_PCI_H
#define __ASM_TX4927_TX4927_PCI_H
#ifndef __ASM_TX4927_TX4927_PCI_H
#define __ASM_TX4927_TX4927_PCI_H
#define TX4927_CCFG_TOE 0x00004000

4
include/asm-mips/vr41xx/vrc4173.h
View File

@@ -21,8 +21,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __NEC_VRC4173_H
#define __NEC_VRC4173_H
#ifndef __NEC_VRC4173_H
#define __NEC_VRC4173_H
#include <linux/config.h>
#include <asm/io.h>

4
include/asm-mips/war.h
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@@ -113,7 +113,7 @@
*/
#define BCM1250_M3_WAR 1
/*
/*
* This is a DUART workaround related to glitches around register accesses
*/
#define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
/*
* Fill buffers not flushed on CACHE instructions
*
*
* Hit_Invalidate_I cacheops invalidate an icache line but the refill
* for that line can get stale data from the fill buffer instead of
* accessing memory if the previous icache miss was also to that line.

2
include/asm-mips/xxs1500.h
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@@ -22,7 +22,7 @@
*
* ########################################################################
*
*
*
*/
#ifndef __ASM_XXS1500_H
#define __ASM_XXS1500_H