ARM: 7448/1: perf: remove arm_perf_pmu_ids global enumeration
In order to provide PMU name strings compatible with the OProfile user ABI, an enumeration of all PMUs is currently used by perf to identify each PMU uniquely. Unfortunately, this does not scale well in the presence of multiple PMUs and creates a single, global namespace across all PMUs in the system. This patch removes the enumeration and instead uses the name string for the PMU to map onto the OProfile variant. perf_pmu_name is implemented for CPU PMUs, which is all that OProfile cares about anyway. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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committed by
Russell King

parent
881ccccb6b
commit
4295b898f5
@@ -47,17 +47,14 @@ static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
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/* Set at runtime when we know what CPU type we are. */
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static struct arm_pmu *cpu_pmu;
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enum arm_perf_pmu_ids
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armpmu_get_pmu_id(void)
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const char *perf_pmu_name(void)
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{
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int id = -ENODEV;
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if (!cpu_pmu)
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return NULL;
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if (cpu_pmu != NULL)
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id = cpu_pmu->id;
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return id;
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return cpu_pmu->pmu.name;
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}
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EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
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EXPORT_SYMBOL_GPL(perf_pmu_name);
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int perf_num_counters(void)
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{
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@@ -760,7 +757,7 @@ init_hw_perf_events(void)
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cpu_pmu->name, cpu_pmu->num_events);
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cpu_pmu_init(cpu_pmu);
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register_cpu_notifier(&pmu_cpu_notifier);
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armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
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armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
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} else {
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pr_info("no hardware support available\n");
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}
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@@ -650,7 +650,6 @@ static int armv6_map_event(struct perf_event *event)
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}
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static struct arm_pmu armv6pmu = {
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.id = ARM_PERF_PMU_ID_V6,
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.name = "v6",
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.handle_irq = armv6pmu_handle_irq,
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.enable = armv6pmu_enable_event,
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@@ -685,7 +684,6 @@ static int armv6mpcore_map_event(struct perf_event *event)
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}
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static struct arm_pmu armv6mpcore_pmu = {
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.id = ARM_PERF_PMU_ID_V6MP,
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.name = "v6mpcore",
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.handle_irq = armv6pmu_handle_irq,
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.enable = armv6pmu_enable_event,
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@@ -1258,7 +1258,6 @@ static u32 __init armv7_read_num_pmnc_events(void)
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static struct arm_pmu *__init armv7_a8_pmu_init(void)
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{
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armv7pmu.id = ARM_PERF_PMU_ID_CA8;
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armv7pmu.name = "ARMv7 Cortex-A8";
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armv7pmu.map_event = armv7_a8_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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@@ -1267,7 +1266,6 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
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static struct arm_pmu *__init armv7_a9_pmu_init(void)
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{
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armv7pmu.id = ARM_PERF_PMU_ID_CA9;
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armv7pmu.name = "ARMv7 Cortex-A9";
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armv7pmu.map_event = armv7_a9_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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@@ -1276,7 +1274,6 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
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static struct arm_pmu *__init armv7_a5_pmu_init(void)
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{
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armv7pmu.id = ARM_PERF_PMU_ID_CA5;
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armv7pmu.name = "ARMv7 Cortex-A5";
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armv7pmu.map_event = armv7_a5_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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@@ -1285,7 +1282,6 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
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static struct arm_pmu *__init armv7_a15_pmu_init(void)
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{
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armv7pmu.id = ARM_PERF_PMU_ID_CA15;
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armv7pmu.name = "ARMv7 Cortex-A15";
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armv7pmu.map_event = armv7_a15_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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@@ -1295,7 +1291,6 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
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static struct arm_pmu *__init armv7_a7_pmu_init(void)
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{
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armv7pmu.id = ARM_PERF_PMU_ID_CA7;
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armv7pmu.name = "ARMv7 Cortex-A7";
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armv7pmu.map_event = armv7_a7_map_event;
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armv7pmu.num_events = armv7_read_num_pmnc_events();
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@@ -435,7 +435,6 @@ static int xscale_map_event(struct perf_event *event)
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}
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static struct arm_pmu xscale1pmu = {
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.id = ARM_PERF_PMU_ID_XSCALE1,
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.name = "xscale1",
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.handle_irq = xscale1pmu_handle_irq,
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.enable = xscale1pmu_enable_event,
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@@ -803,7 +802,6 @@ xscale2pmu_write_counter(int counter, u32 val)
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}
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static struct arm_pmu xscale2pmu = {
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.id = ARM_PERF_PMU_ID_XSCALE2,
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.name = "xscale2",
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.handle_irq = xscale2pmu_handle_irq,
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.enable = xscale2pmu_enable_event,
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