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firmware: xilinx: Use APIs instead of IOCTLs

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Remove IOCTL API and use individual APIs for better readability.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Link: https://lore.kernel.org/r/1587761887-4279-12-git-send-email-jolly.shah@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
此提交包含在：
Rajan Vaja
2020-04-24 13:57:53 -07:00
提交者 Greg Kroah-Hartman
父節點 70c0d36462
當前提交 426c8d85df
共有 4 個檔案被更改，包括 132 行新增 和 81 行删除
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38
drivers/mmc/host/sdhci-of-arasan.c
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@@ -98,10 +98,6 @@ struct sdhci_arasan_clk_data {
void *clk_of_data;
};
struct sdhci_arasan_zynqmp_clk_data {
const struct zynqmp_eemi_ops *eemi_ops;
};
/**
* struct sdhci_arasan_data
* @host: Pointer to the main SDHCI host structure.
@@ -630,9 +626,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
struct sdhci_arasan_data *sdhci_arasan =
container_of(clk_data, struct sdhci_arasan_data, clk_data);
struct sdhci_host *host = sdhci_arasan->host;
struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
clk_data->clk_of_data;
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
const char *clk_name = clk_hw_get_name(hw);
u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
u8 tap_delay, tap_max = 0;
@@ -672,8 +665,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
tap_delay = (degrees * tap_max) / 360;
/* Set the Clock Phase */
ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_OUTPUT, tap_delay, NULL);
ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
if (ret)
pr_err("Error setting Output Tap Delay\n");
@@ -702,9 +694,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
struct sdhci_arasan_data *sdhci_arasan =
container_of(clk_data, struct sdhci_arasan_data, clk_data);
struct sdhci_host *host = sdhci_arasan->host;
struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
clk_data->clk_of_data;
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
const char *clk_name = clk_hw_get_name(hw);
u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
u8 tap_delay, tap_max = 0;
@@ -744,8 +733,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
tap_delay = (degrees * tap_max) / 360;
/* Set the Clock Phase */
ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_INPUT, tap_delay, NULL);
ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
if (ret)
pr_err("Error setting Input Tap Delay\n");
@@ -759,11 +747,6 @@ static const struct clk_ops zynqmp_sampleclk_ops = {
static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
sdhci_arasan->clk_data.clk_of_data;
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
u16 clk;
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
@@ -771,8 +754,7 @@ static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
/* Issue DLL Reset */
eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET,
PM_DLL_RESET_PULSE, 0, NULL);
zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
@@ -1277,20 +1259,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_disable_all;
if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data;
const struct zynqmp_eemi_ops *eemi_ops;
zynqmp_clk_data = devm_kzalloc(&pdev->dev,
sizeof(*zynqmp_clk_data),
GFP_KERNEL);
eemi_ops = zynqmp_pm_get_eemi_ops();
if (IS_ERR(eemi_ops)) {
ret = PTR_ERR(eemi_ops);
goto unreg_clk;
}
zynqmp_clk_data->eemi_ops = eemi_ops;
sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data;
host->mmc_host_ops.execute_tuning =
arasan_zynqmp_execute_tuning;
}