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x86/oprofile: replace CTR_OVERFLOWED macros

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The patch replaces all CTR_OVERFLOWED macros. 64 bit MSR functions and
64 bit counter values are used now. Thus, it will be easier to later
extend the models to use more than 32 bit width counters.

Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter
2009-05-25 17:59:06 +02:00
parent 3370d35856
commit 42399adb23
3 changed files with 15 additions and 17 deletions
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16
arch/x86/oprofile/op_model_amd.c
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@@ -26,11 +26,10 @@
#define NUM_COUNTERS 4
#define NUM_CONTROLS 4
#define OP_EVENT_MASK 0x0FFF
#define OP_CTR_OVERFLOW (1ULL<<31)
#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
static unsigned long reset_value[NUM_COUNTERS];
#ifdef CONFIG_OPROFILE_IBS
@@ -241,17 +240,18 @@ static inline void op_amd_stop_ibs(void) { }
static int op_amd_check_ctrs(struct pt_regs * const regs,
struct op_msrs const * const msrs)
{
unsigned int low, high;
u64 val;
int i;
for (i = 0 ; i < NUM_COUNTERS; ++i) {
if (!reset_value[i])
continue;
rdmsr(msrs->counters[i].addr, low, high);
if (CTR_OVERFLOWED(low)) {
oprofile_add_sample(regs, i);
wrmsr(msrs->counters[i].addr, -(unsigned int)reset_value[i], -1);
}
rdmsrl(msrs->counters[i].addr, val);
/* bit is clear if overflowed: */
if (val & OP_CTR_OVERFLOW)
continue;
oprofile_add_sample(regs, i);
wrmsr(msrs->counters[i].addr, -(unsigned int)reset_value[i], -1);
}
op_amd_handle_ibs(regs, msrs);