drm/tegra: Move drm to live under host1x
Make drm part of host1x driver. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Tested-by: Erik Faye-Lund <kusmabite@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tento commit je obsažen v:
Terje Bergstrom
odevzdal
Thierry Reding
Thierry Reding
rodič
6236451d83
revize
4231c6b01a
@@ -1,23 +0,0 @@
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config DRM_TEGRA
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tristate "NVIDIA Tegra DRM"
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depends on DRM && OF && ARCH_TEGRA
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select DRM_KMS_HELPER
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select DRM_GEM_CMA_HELPER
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select DRM_KMS_CMA_HELPER
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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help
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Choose this option if you have an NVIDIA Tegra SoC.
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To compile this driver as a module, choose M here: the module
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will be called tegra-drm.
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if DRM_TEGRA
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config DRM_TEGRA_DEBUG
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bool "NVIDIA Tegra DRM debug support"
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help
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Say yes here to enable debugging support.
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endif
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@@ -1,7 +0,0 @@
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ccflags-y := -Iinclude/drm
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ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
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tegra-drm-y := drm.o fb.o dc.o host1x.o
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tegra-drm-y += output.o rgb.o hdmi.o
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obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
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Rozdílový obsah nebyl zobrazen, protože je příliš veliký
Načíst rozdílové porovnání
@@ -1,400 +0,0 @@
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/*
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* Copyright (C) 2012 Avionic Design GmbH
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef TEGRA_DC_H
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#define TEGRA_DC_H 1
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#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
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#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
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#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
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#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
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#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
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#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
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#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
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#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
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#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
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#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
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#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
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#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
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#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
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#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
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#define DC_CMD_DISPLAY_COMMAND 0x032
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#define DISP_CTRL_MODE_STOP (0 << 5)
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#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
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#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
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#define DC_CMD_SIGNAL_RAISE 0x033
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#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
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#define PW0_ENABLE (1 << 0)
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#define PW1_ENABLE (1 << 2)
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#define PW2_ENABLE (1 << 4)
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#define PW3_ENABLE (1 << 6)
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#define PW4_ENABLE (1 << 8)
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#define PM0_ENABLE (1 << 16)
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#define PM1_ENABLE (1 << 18)
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#define DC_CMD_INT_STATUS 0x037
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#define DC_CMD_INT_MASK 0x038
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#define DC_CMD_INT_ENABLE 0x039
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#define DC_CMD_INT_TYPE 0x03a
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#define DC_CMD_INT_POLARITY 0x03b
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#define CTXSW_INT (1 << 0)
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#define FRAME_END_INT (1 << 1)
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#define VBLANK_INT (1 << 2)
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#define WIN_A_UF_INT (1 << 8)
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#define WIN_B_UF_INT (1 << 9)
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#define WIN_C_UF_INT (1 << 10)
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#define WIN_A_OF_INT (1 << 14)
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#define WIN_B_OF_INT (1 << 15)
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#define WIN_C_OF_INT (1 << 16)
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#define DC_CMD_SIGNAL_RAISE1 0x03c
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#define DC_CMD_SIGNAL_RAISE2 0x03d
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#define DC_CMD_SIGNAL_RAISE3 0x03e
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#define DC_CMD_STATE_ACCESS 0x040
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#define READ_MUX (1 << 0)
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#define WRITE_MUX (1 << 2)
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#define DC_CMD_STATE_CONTROL 0x041
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#define GENERAL_ACT_REQ (1 << 0)
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#define WIN_A_ACT_REQ (1 << 1)
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#define WIN_B_ACT_REQ (1 << 2)
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#define WIN_C_ACT_REQ (1 << 3)
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#define GENERAL_UPDATE (1 << 8)
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#define WIN_A_UPDATE (1 << 9)
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#define WIN_B_UPDATE (1 << 10)
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#define WIN_C_UPDATE (1 << 11)
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#define NC_HOST_TRIG (1 << 24)
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#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
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#define WINDOW_A_SELECT (1 << 4)
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#define WINDOW_B_SELECT (1 << 5)
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#define WINDOW_C_SELECT (1 << 6)
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#define DC_CMD_REG_ACT_CONTROL 0x043
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#define DC_COM_CRC_CONTROL 0x300
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#define DC_COM_CRC_CHECKSUM 0x301
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#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
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#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
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#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
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#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
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#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
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#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
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#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
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#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
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#define DC_COM_PIN_MISC_CONTROL 0x31b
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#define DC_COM_PIN_PM0_CONTROL 0x31c
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#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
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#define DC_COM_PIN_PM1_CONTROL 0x31e
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#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
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#define DC_COM_SPI_CONTROL 0x320
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#define DC_COM_SPI_START_BYTE 0x321
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#define DC_COM_HSPI_WRITE_DATA_AB 0x322
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#define DC_COM_HSPI_WRITE_DATA_CD 0x323
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#define DC_COM_HSPI_CS_DC 0x324
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#define DC_COM_SCRATCH_REGISTER_A 0x325
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#define DC_COM_SCRATCH_REGISTER_B 0x326
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#define DC_COM_GPIO_CTRL 0x327
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#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
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#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
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#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
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#define H_PULSE_0_ENABLE (1 << 8)
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#define H_PULSE_1_ENABLE (1 << 10)
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#define H_PULSE_2_ENABLE (1 << 12)
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#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
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#define DC_DISP_DISP_WIN_OPTIONS 0x402
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#define HDMI_ENABLE (1 << 30)
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
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#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
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#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
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#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
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#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
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#define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
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#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
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#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
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#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
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#define DC_DISP_DISP_TIMING_OPTIONS 0x405
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#define VSYNC_H_POSITION(x) ((x) & 0xfff)
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#define DC_DISP_REF_TO_SYNC 0x406
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#define DC_DISP_SYNC_WIDTH 0x407
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#define DC_DISP_BACK_PORCH 0x408
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#define DC_DISP_ACTIVE 0x409
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#define DC_DISP_FRONT_PORCH 0x40a
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#define DC_DISP_H_PULSE0_CONTROL 0x40b
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#define DC_DISP_H_PULSE0_POSITION_A 0x40c
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#define DC_DISP_H_PULSE0_POSITION_B 0x40d
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#define DC_DISP_H_PULSE0_POSITION_C 0x40e
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#define DC_DISP_H_PULSE0_POSITION_D 0x40f
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#define DC_DISP_H_PULSE1_CONTROL 0x410
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#define DC_DISP_H_PULSE1_POSITION_A 0x411
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#define DC_DISP_H_PULSE1_POSITION_B 0x412
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#define DC_DISP_H_PULSE1_POSITION_C 0x413
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#define DC_DISP_H_PULSE1_POSITION_D 0x414
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#define DC_DISP_H_PULSE2_CONTROL 0x415
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#define DC_DISP_H_PULSE2_POSITION_A 0x416
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#define DC_DISP_H_PULSE2_POSITION_B 0x417
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#define DC_DISP_H_PULSE2_POSITION_C 0x418
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#define DC_DISP_H_PULSE2_POSITION_D 0x419
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#define DC_DISP_V_PULSE0_CONTROL 0x41a
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#define DC_DISP_V_PULSE0_POSITION_A 0x41b
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#define DC_DISP_V_PULSE0_POSITION_B 0x41c
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#define DC_DISP_V_PULSE0_POSITION_C 0x41d
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#define DC_DISP_V_PULSE1_CONTROL 0x41e
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#define DC_DISP_V_PULSE1_POSITION_A 0x41f
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#define DC_DISP_V_PULSE1_POSITION_B 0x420
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#define DC_DISP_V_PULSE1_POSITION_C 0x421
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#define DC_DISP_V_PULSE2_CONTROL 0x422
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#define DC_DISP_V_PULSE2_POSITION_A 0x423
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#define DC_DISP_V_PULSE3_CONTROL 0x424
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#define DC_DISP_V_PULSE3_POSITION_A 0x425
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#define DC_DISP_M0_CONTROL 0x426
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#define DC_DISP_M1_CONTROL 0x427
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#define DC_DISP_DI_CONTROL 0x428
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#define DC_DISP_PP_CONTROL 0x429
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#define DC_DISP_PP_SELECT_A 0x42a
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#define DC_DISP_PP_SELECT_B 0x42b
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#define DC_DISP_PP_SELECT_C 0x42c
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#define DC_DISP_PP_SELECT_D 0x42d
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#define PULSE_MODE_NORMAL (0 << 3)
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#define PULSE_MODE_ONE_CLOCK (1 << 3)
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#define PULSE_POLARITY_HIGH (0 << 4)
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#define PULSE_POLARITY_LOW (1 << 4)
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#define PULSE_QUAL_ALWAYS (0 << 6)
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#define PULSE_QUAL_VACTIVE (2 << 6)
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#define PULSE_QUAL_VACTIVE1 (3 << 6)
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#define PULSE_LAST_START_A (0 << 8)
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#define PULSE_LAST_END_A (1 << 8)
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#define PULSE_LAST_START_B (2 << 8)
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#define PULSE_LAST_END_B (3 << 8)
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#define PULSE_LAST_START_C (4 << 8)
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#define PULSE_LAST_END_C (5 << 8)
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#define PULSE_LAST_START_D (6 << 8)
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#define PULSE_LAST_END_D (7 << 8)
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#define PULSE_START(x) (((x) & 0xfff) << 0)
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#define PULSE_END(x) (((x) & 0xfff) << 16)
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#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
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#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
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#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
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#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
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#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
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#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
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#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
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#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
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#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
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#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
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#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
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#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
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#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
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#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
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#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
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#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
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#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
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#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
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#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
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#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
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#define DISP_DATA_FORMAT_DF2S (4 << 0)
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#define DISP_DATA_FORMAT_DF3S (5 << 0)
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#define DISP_DATA_FORMAT_DFSPI (6 << 0)
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#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
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#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
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#define DISP_ALIGNMENT_MSB (0 << 8)
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#define DISP_ALIGNMENT_LSB (1 << 8)
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#define DISP_ORDER_RED_BLUE (0 << 9)
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#define DISP_ORDER_BLUE_RED (1 << 9)
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#define DC_DISP_DISP_COLOR_CONTROL 0x430
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#define BASE_COLOR_SIZE666 (0 << 0)
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#define BASE_COLOR_SIZE111 (1 << 0)
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#define BASE_COLOR_SIZE222 (2 << 0)
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#define BASE_COLOR_SIZE333 (3 << 0)
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#define BASE_COLOR_SIZE444 (4 << 0)
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#define BASE_COLOR_SIZE555 (5 << 0)
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#define BASE_COLOR_SIZE565 (6 << 0)
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#define BASE_COLOR_SIZE332 (7 << 0)
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#define BASE_COLOR_SIZE888 (8 << 0)
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#define DITHER_CONTROL_DISABLE (0 << 8)
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#define DITHER_CONTROL_ORDERED (2 << 8)
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#define DITHER_CONTROL_ERRDIFF (3 << 8)
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#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
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#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
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#define DE_SELECT_ACTIVE_BLANK (0 << 0)
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#define DE_SELECT_ACTIVE (1 << 0)
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#define DE_SELECT_ACTIVE_IS (2 << 0)
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#define DE_CONTROL_ONECLK (0 << 2)
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#define DE_CONTROL_NORMAL (1 << 2)
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#define DE_CONTROL_EARLY_EXT (2 << 2)
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#define DE_CONTROL_EARLY (3 << 2)
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#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
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#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
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#define DC_DISP_LCD_SPI_OPTIONS 0x434
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#define DC_DISP_BORDER_COLOR 0x435
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#define DC_DISP_COLOR_KEY0_LOWER 0x436
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#define DC_DISP_COLOR_KEY0_UPPER 0x437
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#define DC_DISP_COLOR_KEY1_LOWER 0x438
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#define DC_DISP_COLOR_KEY1_UPPER 0x439
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#define DC_DISP_CURSOR_FOREGROUND 0x43c
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#define DC_DISP_CURSOR_BACKGROUND 0x43d
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#define DC_DISP_CURSOR_START_ADDR 0x43e
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#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
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#define DC_DISP_CURSOR_POSITION 0x440
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#define DC_DISP_CURSOR_POSITION_NS 0x441
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#define DC_DISP_INIT_SEQ_CONTROL 0x442
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#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
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#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
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#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
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#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
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#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
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#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
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#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
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#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
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#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
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#define DC_DISP_DAC_CRT_CTRL 0x4c0
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#define DC_DISP_DISP_MISC_CONTROL 0x4c1
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#define DC_DISP_SD_CONTROL 0x4c2
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#define DC_DISP_SD_CSC_COEFF 0x4c3
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#define DC_DISP_SD_LUT(x) (0x4c4 + (x))
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#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
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#define DC_DISP_DC_PIXEL_COUNT 0x4ce
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#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
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#define DC_DISP_SD_BL_PARAMETERS 0x4d7
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#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
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#define DC_DISP_SD_BL_CONTROL 0x4dc
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#define DC_DISP_SD_HW_K_VALUES 0x4dd
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#define DC_DISP_SD_MAN_K_VALUES 0x4de
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#define DC_WIN_CSC_YOF 0x611
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||||
#define DC_WIN_CSC_KYRGB 0x612
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||||
#define DC_WIN_CSC_KUR 0x613
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#define DC_WIN_CSC_KVR 0x614
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#define DC_WIN_CSC_KUG 0x615
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||||
#define DC_WIN_CSC_KVG 0x616
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||||
#define DC_WIN_CSC_KUB 0x617
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#define DC_WIN_CSC_KVB 0x618
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||||
#define DC_WIN_WIN_OPTIONS 0x700
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||||
#define COLOR_EXPAND (1 << 6)
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||||
#define CSC_ENABLE (1 << 18)
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||||
#define WIN_ENABLE (1 << 30)
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#define DC_WIN_BYTE_SWAP 0x701
|
||||
#define BYTE_SWAP_NOSWAP (0 << 0)
|
||||
#define BYTE_SWAP_SWAP2 (1 << 0)
|
||||
#define BYTE_SWAP_SWAP4 (2 << 0)
|
||||
#define BYTE_SWAP_SWAP4HW (3 << 0)
|
||||
|
||||
#define DC_WIN_BUFFER_CONTROL 0x702
|
||||
#define BUFFER_CONTROL_HOST (0 << 0)
|
||||
#define BUFFER_CONTROL_VI (1 << 0)
|
||||
#define BUFFER_CONTROL_EPP (2 << 0)
|
||||
#define BUFFER_CONTROL_MPEGE (3 << 0)
|
||||
#define BUFFER_CONTROL_SB2D (4 << 0)
|
||||
|
||||
#define DC_WIN_COLOR_DEPTH 0x703
|
||||
#define WIN_COLOR_DEPTH_P1 0
|
||||
#define WIN_COLOR_DEPTH_P2 1
|
||||
#define WIN_COLOR_DEPTH_P4 2
|
||||
#define WIN_COLOR_DEPTH_P8 3
|
||||
#define WIN_COLOR_DEPTH_B4G4R4A4 4
|
||||
#define WIN_COLOR_DEPTH_B5G5R5A 5
|
||||
#define WIN_COLOR_DEPTH_B5G6R5 6
|
||||
#define WIN_COLOR_DEPTH_AB5G5R5 7
|
||||
#define WIN_COLOR_DEPTH_B8G8R8A8 12
|
||||
#define WIN_COLOR_DEPTH_R8G8B8A8 13
|
||||
#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
|
||||
#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
|
||||
#define WIN_COLOR_DEPTH_YCbCr422 16
|
||||
#define WIN_COLOR_DEPTH_YUV422 17
|
||||
#define WIN_COLOR_DEPTH_YCbCr420P 18
|
||||
#define WIN_COLOR_DEPTH_YUV420P 19
|
||||
#define WIN_COLOR_DEPTH_YCbCr422P 20
|
||||
#define WIN_COLOR_DEPTH_YUV422P 21
|
||||
#define WIN_COLOR_DEPTH_YCbCr422R 22
|
||||
#define WIN_COLOR_DEPTH_YUV422R 23
|
||||
#define WIN_COLOR_DEPTH_YCbCr422RA 24
|
||||
#define WIN_COLOR_DEPTH_YUV422RA 25
|
||||
|
||||
#define DC_WIN_POSITION 0x704
|
||||
#define H_POSITION(x) (((x) & 0x1fff) << 0)
|
||||
#define V_POSITION(x) (((x) & 0x1fff) << 16)
|
||||
|
||||
#define DC_WIN_SIZE 0x705
|
||||
#define H_SIZE(x) (((x) & 0x1fff) << 0)
|
||||
#define V_SIZE(x) (((x) & 0x1fff) << 16)
|
||||
|
||||
#define DC_WIN_PRESCALED_SIZE 0x706
|
||||
#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
|
||||
#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
|
||||
|
||||
#define DC_WIN_H_INITIAL_DDA 0x707
|
||||
#define DC_WIN_V_INITIAL_DDA 0x708
|
||||
#define DC_WIN_DDA_INC 0x709
|
||||
#define H_DDA_INC(x) (((x) & 0xffff) << 0)
|
||||
#define V_DDA_INC(x) (((x) & 0xffff) << 16)
|
||||
|
||||
#define DC_WIN_LINE_STRIDE 0x70a
|
||||
#define DC_WIN_BUF_STRIDE 0x70b
|
||||
#define DC_WIN_UV_BUF_STRIDE 0x70c
|
||||
#define DC_WIN_BUFFER_ADDR_MODE 0x70d
|
||||
#define DC_WIN_DV_CONTROL 0x70e
|
||||
|
||||
#define DC_WIN_BLEND_NOKEY 0x70f
|
||||
#define DC_WIN_BLEND_1WIN 0x710
|
||||
#define DC_WIN_BLEND_2WIN_X 0x711
|
||||
#define DC_WIN_BLEND_2WIN_Y 0x712
|
||||
#define DC_WIN_BLEND_3WIN_XY 0x713
|
||||
|
||||
#define DC_WIN_HP_FETCH_CONTROL 0x714
|
||||
|
||||
#define DC_WINBUF_START_ADDR 0x800
|
||||
#define DC_WINBUF_START_ADDR_NS 0x801
|
||||
#define DC_WINBUF_START_ADDR_U 0x802
|
||||
#define DC_WINBUF_START_ADDR_U_NS 0x803
|
||||
#define DC_WINBUF_START_ADDR_V 0x804
|
||||
#define DC_WINBUF_START_ADDR_V_NS 0x805
|
||||
|
||||
#define DC_WINBUF_ADDR_H_OFFSET 0x806
|
||||
#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
|
||||
#define DC_WINBUF_ADDR_V_OFFSET 0x808
|
||||
#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
|
||||
|
||||
#define DC_WINBUF_UFLOW_STATUS 0x80a
|
||||
|
||||
#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
|
||||
#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
|
||||
#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
|
||||
|
||||
/* synchronization points */
|
||||
#define SYNCPT_VBLANK0 26
|
||||
#define SYNCPT_VBLANK1 27
|
||||
|
||||
#endif /* TEGRA_DC_H */
|
||||
@@ -1,217 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/dma-iommu.h>
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#define DRIVER_NAME "tegra"
|
||||
#define DRIVER_DESC "NVIDIA Tegra graphics"
|
||||
#define DRIVER_DATE "20120330"
|
||||
#define DRIVER_MAJOR 0
|
||||
#define DRIVER_MINOR 0
|
||||
#define DRIVER_PATCHLEVEL 0
|
||||
|
||||
static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
|
||||
{
|
||||
struct device *dev = drm->dev;
|
||||
struct host1x *host1x;
|
||||
int err;
|
||||
|
||||
host1x = dev_get_drvdata(dev);
|
||||
drm->dev_private = host1x;
|
||||
host1x->drm = drm;
|
||||
|
||||
drm_mode_config_init(drm);
|
||||
|
||||
err = host1x_drm_init(host1x, drm);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = drm_vblank_init(drm, drm->mode_config.num_crtc);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = tegra_drm_fb_init(drm);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
drm_kms_helper_poll_init(drm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drm_unload(struct drm_device *drm)
|
||||
{
|
||||
drm_kms_helper_poll_fini(drm);
|
||||
tegra_drm_fb_exit(drm);
|
||||
|
||||
drm_mode_config_cleanup(drm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_drm_lastclose(struct drm_device *drm)
|
||||
{
|
||||
struct host1x *host1x = drm->dev_private;
|
||||
|
||||
drm_fbdev_cma_restore_mode(host1x->fbdev);
|
||||
}
|
||||
|
||||
static struct drm_ioctl_desc tegra_drm_ioctls[] = {
|
||||
};
|
||||
|
||||
static const struct file_operations tegra_drm_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = drm_open,
|
||||
.release = drm_release,
|
||||
.unlocked_ioctl = drm_ioctl,
|
||||
.mmap = drm_gem_cma_mmap,
|
||||
.poll = drm_poll,
|
||||
.fasync = drm_fasync,
|
||||
.read = drm_read,
|
||||
#ifdef CONFIG_COMPAT
|
||||
.compat_ioctl = drm_compat_ioctl,
|
||||
#endif
|
||||
.llseek = noop_llseek,
|
||||
};
|
||||
|
||||
static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, int pipe)
|
||||
{
|
||||
struct drm_crtc *crtc;
|
||||
|
||||
list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) {
|
||||
struct tegra_dc *dc = to_tegra_dc(crtc);
|
||||
|
||||
if (dc->pipe == pipe)
|
||||
return crtc;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static u32 tegra_drm_get_vblank_counter(struct drm_device *dev, int crtc)
|
||||
{
|
||||
/* TODO: implement real hardware counter using syncpoints */
|
||||
return drm_vblank_count(dev, crtc);
|
||||
}
|
||||
|
||||
static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe)
|
||||
{
|
||||
struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe);
|
||||
struct tegra_dc *dc = to_tegra_dc(crtc);
|
||||
|
||||
if (!crtc)
|
||||
return -ENODEV;
|
||||
|
||||
tegra_dc_enable_vblank(dc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_drm_disable_vblank(struct drm_device *drm, int pipe)
|
||||
{
|
||||
struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe);
|
||||
struct tegra_dc *dc = to_tegra_dc(crtc);
|
||||
|
||||
if (crtc)
|
||||
tegra_dc_disable_vblank(dc);
|
||||
}
|
||||
|
||||
static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
|
||||
{
|
||||
struct drm_crtc *crtc;
|
||||
|
||||
list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
|
||||
tegra_dc_cancel_page_flip(crtc, file);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
|
||||
{
|
||||
struct drm_info_node *node = (struct drm_info_node *)s->private;
|
||||
struct drm_device *drm = node->minor->dev;
|
||||
struct drm_framebuffer *fb;
|
||||
|
||||
mutex_lock(&drm->mode_config.fb_lock);
|
||||
|
||||
list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
|
||||
seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
|
||||
fb->base.id, fb->width, fb->height, fb->depth,
|
||||
fb->bits_per_pixel,
|
||||
atomic_read(&fb->refcount.refcount));
|
||||
}
|
||||
|
||||
mutex_unlock(&drm->mode_config.fb_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct drm_info_list tegra_debugfs_list[] = {
|
||||
{ "framebuffers", tegra_debugfs_framebuffers, 0 },
|
||||
};
|
||||
|
||||
static int tegra_debugfs_init(struct drm_minor *minor)
|
||||
{
|
||||
return drm_debugfs_create_files(tegra_debugfs_list,
|
||||
ARRAY_SIZE(tegra_debugfs_list),
|
||||
minor->debugfs_root, minor);
|
||||
}
|
||||
|
||||
static void tegra_debugfs_cleanup(struct drm_minor *minor)
|
||||
{
|
||||
drm_debugfs_remove_files(tegra_debugfs_list,
|
||||
ARRAY_SIZE(tegra_debugfs_list), minor);
|
||||
}
|
||||
#endif
|
||||
|
||||
struct drm_driver tegra_drm_driver = {
|
||||
.driver_features = DRIVER_BUS_PLATFORM | DRIVER_MODESET | DRIVER_GEM,
|
||||
.load = tegra_drm_load,
|
||||
.unload = tegra_drm_unload,
|
||||
.open = tegra_drm_open,
|
||||
.preclose = tegra_drm_preclose,
|
||||
.lastclose = tegra_drm_lastclose,
|
||||
|
||||
.get_vblank_counter = tegra_drm_get_vblank_counter,
|
||||
.enable_vblank = tegra_drm_enable_vblank,
|
||||
.disable_vblank = tegra_drm_disable_vblank,
|
||||
|
||||
#if defined(CONFIG_DEBUG_FS)
|
||||
.debugfs_init = tegra_debugfs_init,
|
||||
.debugfs_cleanup = tegra_debugfs_cleanup,
|
||||
#endif
|
||||
|
||||
.gem_free_object = drm_gem_cma_free_object,
|
||||
.gem_vm_ops = &drm_gem_cma_vm_ops,
|
||||
.dumb_create = drm_gem_cma_dumb_create,
|
||||
.dumb_map_offset = drm_gem_cma_dumb_map_offset,
|
||||
.dumb_destroy = drm_gem_cma_dumb_destroy,
|
||||
|
||||
.ioctls = tegra_drm_ioctls,
|
||||
.num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
|
||||
.fops = &tegra_drm_fops,
|
||||
|
||||
.name = DRIVER_NAME,
|
||||
.desc = DRIVER_DESC,
|
||||
.date = DRIVER_DATE,
|
||||
.major = DRIVER_MAJOR,
|
||||
.minor = DRIVER_MINOR,
|
||||
.patchlevel = DRIVER_PATCHLEVEL,
|
||||
};
|
||||
@@ -1,237 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef TEGRA_DRM_H
|
||||
#define TEGRA_DRM_H 1
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#include <drm/drm_gem_cma_helper.h>
|
||||
#include <drm/drm_fb_cma_helper.h>
|
||||
#include <drm/drm_fixed.h>
|
||||
|
||||
struct host1x {
|
||||
struct drm_device *drm;
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct clk *clk;
|
||||
int syncpt;
|
||||
int irq;
|
||||
|
||||
struct mutex drm_clients_lock;
|
||||
struct list_head drm_clients;
|
||||
struct list_head drm_active;
|
||||
|
||||
struct mutex clients_lock;
|
||||
struct list_head clients;
|
||||
|
||||
struct drm_fbdev_cma *fbdev;
|
||||
};
|
||||
|
||||
struct host1x_client;
|
||||
|
||||
struct host1x_client_ops {
|
||||
int (*drm_init)(struct host1x_client *client, struct drm_device *drm);
|
||||
int (*drm_exit)(struct host1x_client *client);
|
||||
};
|
||||
|
||||
struct host1x_client {
|
||||
struct host1x *host1x;
|
||||
struct device *dev;
|
||||
|
||||
const struct host1x_client_ops *ops;
|
||||
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
extern int host1x_drm_init(struct host1x *host1x, struct drm_device *drm);
|
||||
extern int host1x_drm_exit(struct host1x *host1x);
|
||||
|
||||
extern int host1x_register_client(struct host1x *host1x,
|
||||
struct host1x_client *client);
|
||||
extern int host1x_unregister_client(struct host1x *host1x,
|
||||
struct host1x_client *client);
|
||||
|
||||
struct tegra_output;
|
||||
|
||||
struct tegra_dc {
|
||||
struct host1x_client client;
|
||||
spinlock_t lock;
|
||||
|
||||
struct host1x *host1x;
|
||||
struct device *dev;
|
||||
|
||||
struct drm_crtc base;
|
||||
int pipe;
|
||||
|
||||
struct clk *clk;
|
||||
|
||||
void __iomem *regs;
|
||||
int irq;
|
||||
|
||||
struct tegra_output *rgb;
|
||||
|
||||
struct list_head list;
|
||||
|
||||
struct drm_info_list *debugfs_files;
|
||||
struct drm_minor *minor;
|
||||
struct dentry *debugfs;
|
||||
|
||||
/* page-flip handling */
|
||||
struct drm_pending_vblank_event *event;
|
||||
};
|
||||
|
||||
static inline struct tegra_dc *host1x_client_to_dc(struct host1x_client *client)
|
||||
{
|
||||
return container_of(client, struct tegra_dc, client);
|
||||
}
|
||||
|
||||
static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
|
||||
{
|
||||
return container_of(crtc, struct tegra_dc, base);
|
||||
}
|
||||
|
||||
static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value,
|
||||
unsigned long reg)
|
||||
{
|
||||
writel(value, dc->regs + (reg << 2));
|
||||
}
|
||||
|
||||
static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
|
||||
unsigned long reg)
|
||||
{
|
||||
return readl(dc->regs + (reg << 2));
|
||||
}
|
||||
|
||||
struct tegra_dc_window {
|
||||
struct {
|
||||
unsigned int x;
|
||||
unsigned int y;
|
||||
unsigned int w;
|
||||
unsigned int h;
|
||||
} src;
|
||||
struct {
|
||||
unsigned int x;
|
||||
unsigned int y;
|
||||
unsigned int w;
|
||||
unsigned int h;
|
||||
} dst;
|
||||
unsigned int bits_per_pixel;
|
||||
unsigned int format;
|
||||
unsigned int stride[2];
|
||||
unsigned long base[3];
|
||||
};
|
||||
|
||||
/* from dc.c */
|
||||
extern unsigned int tegra_dc_format(uint32_t format);
|
||||
extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
|
||||
const struct tegra_dc_window *window);
|
||||
extern void tegra_dc_enable_vblank(struct tegra_dc *dc);
|
||||
extern void tegra_dc_disable_vblank(struct tegra_dc *dc);
|
||||
extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc,
|
||||
struct drm_file *file);
|
||||
|
||||
struct tegra_output_ops {
|
||||
int (*enable)(struct tegra_output *output);
|
||||
int (*disable)(struct tegra_output *output);
|
||||
int (*setup_clock)(struct tegra_output *output, struct clk *clk,
|
||||
unsigned long pclk);
|
||||
int (*check_mode)(struct tegra_output *output,
|
||||
struct drm_display_mode *mode,
|
||||
enum drm_mode_status *status);
|
||||
};
|
||||
|
||||
enum tegra_output_type {
|
||||
TEGRA_OUTPUT_RGB,
|
||||
TEGRA_OUTPUT_HDMI,
|
||||
};
|
||||
|
||||
struct tegra_output {
|
||||
struct device_node *of_node;
|
||||
struct device *dev;
|
||||
|
||||
const struct tegra_output_ops *ops;
|
||||
enum tegra_output_type type;
|
||||
|
||||
struct i2c_adapter *ddc;
|
||||
const struct edid *edid;
|
||||
unsigned int hpd_irq;
|
||||
int hpd_gpio;
|
||||
|
||||
struct drm_encoder encoder;
|
||||
struct drm_connector connector;
|
||||
};
|
||||
|
||||
static inline struct tegra_output *encoder_to_output(struct drm_encoder *e)
|
||||
{
|
||||
return container_of(e, struct tegra_output, encoder);
|
||||
}
|
||||
|
||||
static inline struct tegra_output *connector_to_output(struct drm_connector *c)
|
||||
{
|
||||
return container_of(c, struct tegra_output, connector);
|
||||
}
|
||||
|
||||
static inline int tegra_output_enable(struct tegra_output *output)
|
||||
{
|
||||
if (output && output->ops && output->ops->enable)
|
||||
return output->ops->enable(output);
|
||||
|
||||
return output ? -ENOSYS : -EINVAL;
|
||||
}
|
||||
|
||||
static inline int tegra_output_disable(struct tegra_output *output)
|
||||
{
|
||||
if (output && output->ops && output->ops->disable)
|
||||
return output->ops->disable(output);
|
||||
|
||||
return output ? -ENOSYS : -EINVAL;
|
||||
}
|
||||
|
||||
static inline int tegra_output_setup_clock(struct tegra_output *output,
|
||||
struct clk *clk, unsigned long pclk)
|
||||
{
|
||||
if (output && output->ops && output->ops->setup_clock)
|
||||
return output->ops->setup_clock(output, clk, pclk);
|
||||
|
||||
return output ? -ENOSYS : -EINVAL;
|
||||
}
|
||||
|
||||
static inline int tegra_output_check_mode(struct tegra_output *output,
|
||||
struct drm_display_mode *mode,
|
||||
enum drm_mode_status *status)
|
||||
{
|
||||
if (output && output->ops && output->ops->check_mode)
|
||||
return output->ops->check_mode(output, mode, status);
|
||||
|
||||
return output ? -ENOSYS : -EINVAL;
|
||||
}
|
||||
|
||||
/* from rgb.c */
|
||||
extern int tegra_dc_rgb_probe(struct tegra_dc *dc);
|
||||
extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
|
||||
extern int tegra_dc_rgb_exit(struct tegra_dc *dc);
|
||||
|
||||
/* from output.c */
|
||||
extern int tegra_output_parse_dt(struct tegra_output *output);
|
||||
extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
|
||||
extern int tegra_output_exit(struct tegra_output *output);
|
||||
|
||||
/* from fb.c */
|
||||
extern int tegra_drm_fb_init(struct drm_device *drm);
|
||||
extern void tegra_drm_fb_exit(struct drm_device *drm);
|
||||
|
||||
extern struct platform_driver tegra_host1x_driver;
|
||||
extern struct platform_driver tegra_hdmi_driver;
|
||||
extern struct platform_driver tegra_dc_driver;
|
||||
extern struct drm_driver tegra_drm_driver;
|
||||
|
||||
#endif /* TEGRA_DRM_H */
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
static void tegra_drm_fb_output_poll_changed(struct drm_device *drm)
|
||||
{
|
||||
struct host1x *host1x = drm->dev_private;
|
||||
|
||||
drm_fbdev_cma_hotplug_event(host1x->fbdev);
|
||||
}
|
||||
|
||||
static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
|
||||
.fb_create = drm_fb_cma_create,
|
||||
.output_poll_changed = tegra_drm_fb_output_poll_changed,
|
||||
};
|
||||
|
||||
int tegra_drm_fb_init(struct drm_device *drm)
|
||||
{
|
||||
struct host1x *host1x = drm->dev_private;
|
||||
struct drm_fbdev_cma *fbdev;
|
||||
|
||||
drm->mode_config.min_width = 0;
|
||||
drm->mode_config.min_height = 0;
|
||||
|
||||
drm->mode_config.max_width = 4096;
|
||||
drm->mode_config.max_height = 4096;
|
||||
|
||||
drm->mode_config.funcs = &tegra_drm_mode_funcs;
|
||||
|
||||
fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
|
||||
drm->mode_config.num_connector);
|
||||
if (IS_ERR(fbdev))
|
||||
return PTR_ERR(fbdev);
|
||||
|
||||
host1x->fbdev = fbdev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_drm_fb_exit(struct drm_device *drm)
|
||||
{
|
||||
struct host1x *host1x = drm->dev_private;
|
||||
|
||||
drm_fbdev_cma_fini(host1x->fbdev);
|
||||
}
|
||||
Rozdílový obsah nebyl zobrazen, protože je příliš veliký
Načíst rozdílové porovnání
@@ -1,386 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef TEGRA_HDMI_H
|
||||
#define TEGRA_HDMI_H 1
|
||||
|
||||
/* register definitions */
|
||||
#define HDMI_CTXSW 0x00
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_STATE0 0x01
|
||||
#define SOR_STATE_UPDATE (1 << 0)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_STATE1 0x02
|
||||
#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
|
||||
#define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
|
||||
#define SOR_STATE_ATTACHED (1 << 3)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_STATE2 0x03
|
||||
#define SOR_STATE_ASY_OWNER_NONE (0 << 0)
|
||||
#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
|
||||
#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
|
||||
#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
|
||||
#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
|
||||
#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
|
||||
#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
|
||||
#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
|
||||
#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
|
||||
#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
|
||||
#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
|
||||
#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
|
||||
#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
|
||||
#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
|
||||
#define SOR_STATE_ASY_DEPOL_POS (0 << 14)
|
||||
#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
|
||||
|
||||
#define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
|
||||
#define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
|
||||
#define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
|
||||
#define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
|
||||
#define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
|
||||
#define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
|
||||
#define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
|
||||
#define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
|
||||
#define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
|
||||
#define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
|
||||
#define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
|
||||
#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
|
||||
#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
|
||||
#define HDMI_NV_PDISP_RG_HDCP_RI 0x17
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
|
||||
#define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
|
||||
#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
|
||||
#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
|
||||
|
||||
#define INFOFRAME_CTRL_ENABLE (1 << 0)
|
||||
|
||||
#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
|
||||
#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
|
||||
#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
|
||||
#define GENERIC_CTRL_ENABLE (1 << 0)
|
||||
#define GENERIC_CTRL_OTHER (1 << 4)
|
||||
#define GENERIC_CTRL_SINGLE (1 << 8)
|
||||
#define GENERIC_CTRL_HBLANK (1 << 12)
|
||||
#define GENERIC_CTRL_AUDIO (1 << 16)
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
|
||||
#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
|
||||
#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
|
||||
|
||||
#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
|
||||
#define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
|
||||
#define ACR_ENABLE (1 << 31)
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_CTRL 0x44
|
||||
#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
|
||||
#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
|
||||
#define HDMI_CTRL_ENABLE (1 << 30)
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
|
||||
#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
|
||||
#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
|
||||
#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
|
||||
#define VSYNC_WINDOW_ENABLE (1 << 31)
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
|
||||
#define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
|
||||
#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
|
||||
#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
|
||||
#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
|
||||
#define HDMI_NV_PDISP_HDMI_EMU0 0x4c
|
||||
#define HDMI_NV_PDISP_HDMI_EMU1 0x4d
|
||||
#define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_SPARE 0x4f
|
||||
#define SPARE_HW_CTS (1 << 0)
|
||||
#define SPARE_FORCE_SW_CTS (1 << 1)
|
||||
#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
|
||||
|
||||
#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
|
||||
#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
|
||||
#define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53
|
||||
#define HDMI_NV_PDISP_SOR_CAP 0x54
|
||||
#define HDMI_NV_PDISP_SOR_PWR 0x55
|
||||
#define SOR_PWR_NORMAL_STATE_PD (0 << 0)
|
||||
#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
|
||||
#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
|
||||
#define SOR_PWR_NORMAL_START_ALT (1 << 1)
|
||||
#define SOR_PWR_SAFE_STATE_PD (0 << 16)
|
||||
#define SOR_PWR_SAFE_STATE_PU (1 << 16)
|
||||
#define SOR_PWR_SETTING_NEW_DONE (0 << 31)
|
||||
#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
|
||||
#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_TEST 0x56
|
||||
#define HDMI_NV_PDISP_SOR_PLL0 0x57
|
||||
#define SOR_PLL_PWR (1 << 0)
|
||||
#define SOR_PLL_PDBG (1 << 1)
|
||||
#define SOR_PLL_VCAPD (1 << 2)
|
||||
#define SOR_PLL_PDPORT (1 << 3)
|
||||
#define SOR_PLL_RESISTORSEL (1 << 4)
|
||||
#define SOR_PLL_PULLDOWN (1 << 5)
|
||||
#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
|
||||
#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
|
||||
#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
|
||||
#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
|
||||
#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_PLL1 0x58
|
||||
#define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
|
||||
#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
|
||||
#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
|
||||
#define SOR_PLL_PE_EN (1 << 28)
|
||||
#define SOR_PLL_HALF_FULL_PE (1 << 29)
|
||||
#define SOR_PLL_S_D_PIN_PE (1 << 30)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_PLL2 0x59
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_CSTM 0x5a
|
||||
#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_LVDS 0x5b
|
||||
#define HDMI_NV_PDISP_SOR_CRCA 0x5c
|
||||
#define HDMI_NV_PDISP_SOR_CRCB 0x5d
|
||||
#define HDMI_NV_PDISP_SOR_BLANK 0x5e
|
||||
#define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
|
||||
#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0)
|
||||
#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
|
||||
#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
|
||||
#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
|
||||
#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
|
||||
#define SOR_SEQ_STATUS (1 << 28)
|
||||
#define SOR_SEQ_SWITCH (1 << 30)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x))
|
||||
|
||||
#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
|
||||
#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
|
||||
#define SOR_SEQ_INST_HALT (1 << 15)
|
||||
#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
|
||||
#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
|
||||
#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
|
||||
#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
|
||||
#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_VCRCA0 0x72
|
||||
#define HDMI_NV_PDISP_SOR_VCRCA1 0x73
|
||||
#define HDMI_NV_PDISP_SOR_CCRCA0 0x74
|
||||
#define HDMI_NV_PDISP_SOR_CCRCA1 0x75
|
||||
#define HDMI_NV_PDISP_SOR_EDATAA0 0x76
|
||||
#define HDMI_NV_PDISP_SOR_EDATAA1 0x77
|
||||
#define HDMI_NV_PDISP_SOR_COUNTA0 0x78
|
||||
#define HDMI_NV_PDISP_SOR_COUNTA1 0x79
|
||||
#define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
|
||||
#define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
|
||||
#define HDMI_NV_PDISP_SOR_TRIG 0x7c
|
||||
#define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
|
||||
#define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
|
||||
#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
|
||||
#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
|
||||
#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
|
||||
#define DRIVE_CURRENT_FUSE_OVERRIDE (1 << 31)
|
||||
|
||||
#define DRIVE_CURRENT_1_500_mA 0x00
|
||||
#define DRIVE_CURRENT_1_875_mA 0x01
|
||||
#define DRIVE_CURRENT_2_250_mA 0x02
|
||||
#define DRIVE_CURRENT_2_625_mA 0x03
|
||||
#define DRIVE_CURRENT_3_000_mA 0x04
|
||||
#define DRIVE_CURRENT_3_375_mA 0x05
|
||||
#define DRIVE_CURRENT_3_750_mA 0x06
|
||||
#define DRIVE_CURRENT_4_125_mA 0x07
|
||||
#define DRIVE_CURRENT_4_500_mA 0x08
|
||||
#define DRIVE_CURRENT_4_875_mA 0x09
|
||||
#define DRIVE_CURRENT_5_250_mA 0x0a
|
||||
#define DRIVE_CURRENT_5_625_mA 0x0b
|
||||
#define DRIVE_CURRENT_6_000_mA 0x0c
|
||||
#define DRIVE_CURRENT_6_375_mA 0x0d
|
||||
#define DRIVE_CURRENT_6_750_mA 0x0e
|
||||
#define DRIVE_CURRENT_7_125_mA 0x0f
|
||||
#define DRIVE_CURRENT_7_500_mA 0x10
|
||||
#define DRIVE_CURRENT_7_875_mA 0x11
|
||||
#define DRIVE_CURRENT_8_250_mA 0x12
|
||||
#define DRIVE_CURRENT_8_625_mA 0x13
|
||||
#define DRIVE_CURRENT_9_000_mA 0x14
|
||||
#define DRIVE_CURRENT_9_375_mA 0x15
|
||||
#define DRIVE_CURRENT_9_750_mA 0x16
|
||||
#define DRIVE_CURRENT_10_125_mA 0x17
|
||||
#define DRIVE_CURRENT_10_500_mA 0x18
|
||||
#define DRIVE_CURRENT_10_875_mA 0x19
|
||||
#define DRIVE_CURRENT_11_250_mA 0x1a
|
||||
#define DRIVE_CURRENT_11_625_mA 0x1b
|
||||
#define DRIVE_CURRENT_12_000_mA 0x1c
|
||||
#define DRIVE_CURRENT_12_375_mA 0x1d
|
||||
#define DRIVE_CURRENT_12_750_mA 0x1e
|
||||
#define DRIVE_CURRENT_13_125_mA 0x1f
|
||||
#define DRIVE_CURRENT_13_500_mA 0x20
|
||||
#define DRIVE_CURRENT_13_875_mA 0x21
|
||||
#define DRIVE_CURRENT_14_250_mA 0x22
|
||||
#define DRIVE_CURRENT_14_625_mA 0x23
|
||||
#define DRIVE_CURRENT_15_000_mA 0x24
|
||||
#define DRIVE_CURRENT_15_375_mA 0x25
|
||||
#define DRIVE_CURRENT_15_750_mA 0x26
|
||||
#define DRIVE_CURRENT_16_125_mA 0x27
|
||||
#define DRIVE_CURRENT_16_500_mA 0x28
|
||||
#define DRIVE_CURRENT_16_875_mA 0x29
|
||||
#define DRIVE_CURRENT_17_250_mA 0x2a
|
||||
#define DRIVE_CURRENT_17_625_mA 0x2b
|
||||
#define DRIVE_CURRENT_18_000_mA 0x2c
|
||||
#define DRIVE_CURRENT_18_375_mA 0x2d
|
||||
#define DRIVE_CURRENT_18_750_mA 0x2e
|
||||
#define DRIVE_CURRENT_19_125_mA 0x2f
|
||||
#define DRIVE_CURRENT_19_500_mA 0x30
|
||||
#define DRIVE_CURRENT_19_875_mA 0x31
|
||||
#define DRIVE_CURRENT_20_250_mA 0x32
|
||||
#define DRIVE_CURRENT_20_625_mA 0x33
|
||||
#define DRIVE_CURRENT_21_000_mA 0x34
|
||||
#define DRIVE_CURRENT_21_375_mA 0x35
|
||||
#define DRIVE_CURRENT_21_750_mA 0x36
|
||||
#define DRIVE_CURRENT_22_125_mA 0x37
|
||||
#define DRIVE_CURRENT_22_500_mA 0x38
|
||||
#define DRIVE_CURRENT_22_875_mA 0x39
|
||||
#define DRIVE_CURRENT_23_250_mA 0x3a
|
||||
#define DRIVE_CURRENT_23_625_mA 0x3b
|
||||
#define DRIVE_CURRENT_24_000_mA 0x3c
|
||||
#define DRIVE_CURRENT_24_375_mA 0x3d
|
||||
#define DRIVE_CURRENT_24_750_mA 0x3e
|
||||
|
||||
#define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
|
||||
#define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
|
||||
#define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
|
||||
|
||||
#define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
|
||||
#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
|
||||
#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
|
||||
|
||||
#define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
|
||||
#define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
|
||||
#define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
|
||||
#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
|
||||
#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
|
||||
#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
|
||||
#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
|
||||
#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
|
||||
|
||||
#define HDMI_NV_PDISP_AUDIO_N 0x8c
|
||||
#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
|
||||
#define AUDIO_N_RESETF (1 << 20)
|
||||
#define AUDIO_N_GENERATE_NORMAL (0 << 24)
|
||||
#define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
|
||||
|
||||
#define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
|
||||
#define HDMI_NV_PDISP_SOR_REFCLK 0x95
|
||||
#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
|
||||
#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
|
||||
|
||||
#define HDMI_NV_PDISP_CRC_CONTROL 0x96
|
||||
#define HDMI_NV_PDISP_INPUT_CONTROL 0x97
|
||||
#define HDMI_SRC_DISPLAYA (0 << 0)
|
||||
#define HDMI_SRC_DISPLAYB (1 << 0)
|
||||
#define ARM_VIDEO_RANGE_FULL (0 << 1)
|
||||
#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
|
||||
|
||||
#define HDMI_NV_PDISP_SCRATCH 0x98
|
||||
#define HDMI_NV_PDISP_PE_CURRENT 0x99
|
||||
#define PE_CURRENT0(x) (((x) & 0xf) << 0)
|
||||
#define PE_CURRENT1(x) (((x) & 0xf) << 8)
|
||||
#define PE_CURRENT2(x) (((x) & 0xf) << 16)
|
||||
#define PE_CURRENT3(x) (((x) & 0xf) << 24)
|
||||
|
||||
#define PE_CURRENT_0_0_mA 0x0
|
||||
#define PE_CURRENT_0_5_mA 0x1
|
||||
#define PE_CURRENT_1_0_mA 0x2
|
||||
#define PE_CURRENT_1_5_mA 0x3
|
||||
#define PE_CURRENT_2_0_mA 0x4
|
||||
#define PE_CURRENT_2_5_mA 0x5
|
||||
#define PE_CURRENT_3_0_mA 0x6
|
||||
#define PE_CURRENT_3_5_mA 0x7
|
||||
#define PE_CURRENT_4_0_mA 0x8
|
||||
#define PE_CURRENT_4_5_mA 0x9
|
||||
#define PE_CURRENT_5_0_mA 0xa
|
||||
#define PE_CURRENT_5_5_mA 0xb
|
||||
#define PE_CURRENT_6_0_mA 0xc
|
||||
#define PE_CURRENT_6_5_mA 0xd
|
||||
#define PE_CURRENT_7_0_mA 0xe
|
||||
#define PE_CURRENT_7_5_mA 0xf
|
||||
|
||||
#define HDMI_NV_PDISP_KEY_CTRL 0x9a
|
||||
#define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
|
||||
#define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
|
||||
#define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
|
||||
#define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
|
||||
#define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
|
||||
#define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
|
||||
#define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
|
||||
#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
|
||||
#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac
|
||||
#define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd
|
||||
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
|
||||
#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
|
||||
|
||||
#endif /* TEGRA_HDMI_H */
|
||||
@@ -1,327 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
struct host1x_drm_client {
|
||||
struct host1x_client *client;
|
||||
struct device_node *np;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
static int host1x_add_drm_client(struct host1x *host1x, struct device_node *np)
|
||||
{
|
||||
struct host1x_drm_client *client;
|
||||
|
||||
client = kzalloc(sizeof(*client), GFP_KERNEL);
|
||||
if (!client)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_LIST_HEAD(&client->list);
|
||||
client->np = of_node_get(np);
|
||||
|
||||
list_add_tail(&client->list, &host1x->drm_clients);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int host1x_activate_drm_client(struct host1x *host1x,
|
||||
struct host1x_drm_client *drm,
|
||||
struct host1x_client *client)
|
||||
{
|
||||
mutex_lock(&host1x->drm_clients_lock);
|
||||
list_del_init(&drm->list);
|
||||
list_add_tail(&drm->list, &host1x->drm_active);
|
||||
drm->client = client;
|
||||
mutex_unlock(&host1x->drm_clients_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int host1x_remove_drm_client(struct host1x *host1x,
|
||||
struct host1x_drm_client *client)
|
||||
{
|
||||
mutex_lock(&host1x->drm_clients_lock);
|
||||
list_del_init(&client->list);
|
||||
mutex_unlock(&host1x->drm_clients_lock);
|
||||
|
||||
of_node_put(client->np);
|
||||
kfree(client);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int host1x_parse_dt(struct host1x *host1x)
|
||||
{
|
||||
static const char * const compat[] = {
|
||||
"nvidia,tegra20-dc",
|
||||
"nvidia,tegra20-hdmi",
|
||||
"nvidia,tegra30-dc",
|
||||
"nvidia,tegra30-hdmi",
|
||||
};
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(compat); i++) {
|
||||
struct device_node *np;
|
||||
|
||||
for_each_child_of_node(host1x->dev->of_node, np) {
|
||||
if (of_device_is_compatible(np, compat[i]) &&
|
||||
of_device_is_available(np)) {
|
||||
err = host1x_add_drm_client(host1x, np);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_host1x_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct host1x *host1x;
|
||||
struct resource *regs;
|
||||
int err;
|
||||
|
||||
host1x = devm_kzalloc(&pdev->dev, sizeof(*host1x), GFP_KERNEL);
|
||||
if (!host1x)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&host1x->drm_clients_lock);
|
||||
INIT_LIST_HEAD(&host1x->drm_clients);
|
||||
INIT_LIST_HEAD(&host1x->drm_active);
|
||||
mutex_init(&host1x->clients_lock);
|
||||
INIT_LIST_HEAD(&host1x->clients);
|
||||
host1x->dev = &pdev->dev;
|
||||
|
||||
err = host1x_parse_dt(host1x);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to parse DT: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
host1x->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(host1x->clk))
|
||||
return PTR_ERR(host1x->clk);
|
||||
|
||||
err = clk_prepare_enable(host1x->clk);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!regs) {
|
||||
err = -ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
err = platform_get_irq(pdev, 0);
|
||||
if (err < 0)
|
||||
goto err;
|
||||
|
||||
host1x->syncpt = err;
|
||||
|
||||
err = platform_get_irq(pdev, 1);
|
||||
if (err < 0)
|
||||
goto err;
|
||||
|
||||
host1x->irq = err;
|
||||
|
||||
host1x->regs = devm_ioremap_resource(&pdev->dev, regs);
|
||||
if (IS_ERR(host1x->regs)) {
|
||||
err = PTR_ERR(host1x->regs);
|
||||
goto err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, host1x);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
clk_disable_unprepare(host1x->clk);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tegra_host1x_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct host1x *host1x = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(host1x->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int host1x_drm_init(struct host1x *host1x, struct drm_device *drm)
|
||||
{
|
||||
struct host1x_client *client;
|
||||
|
||||
mutex_lock(&host1x->clients_lock);
|
||||
|
||||
list_for_each_entry(client, &host1x->clients, list) {
|
||||
if (client->ops && client->ops->drm_init) {
|
||||
int err = client->ops->drm_init(client, drm);
|
||||
if (err < 0) {
|
||||
dev_err(host1x->dev,
|
||||
"DRM setup failed for %s: %d\n",
|
||||
dev_name(client->dev), err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&host1x->clients_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int host1x_drm_exit(struct host1x *host1x)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(host1x->dev);
|
||||
struct host1x_client *client;
|
||||
|
||||
if (!host1x->drm)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&host1x->clients_lock);
|
||||
|
||||
list_for_each_entry_reverse(client, &host1x->clients, list) {
|
||||
if (client->ops && client->ops->drm_exit) {
|
||||
int err = client->ops->drm_exit(client);
|
||||
if (err < 0) {
|
||||
dev_err(host1x->dev,
|
||||
"DRM cleanup failed for %s: %d\n",
|
||||
dev_name(client->dev), err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&host1x->clients_lock);
|
||||
|
||||
drm_platform_exit(&tegra_drm_driver, pdev);
|
||||
host1x->drm = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int host1x_register_client(struct host1x *host1x, struct host1x_client *client)
|
||||
{
|
||||
struct host1x_drm_client *drm, *tmp;
|
||||
int err;
|
||||
|
||||
mutex_lock(&host1x->clients_lock);
|
||||
list_add_tail(&client->list, &host1x->clients);
|
||||
mutex_unlock(&host1x->clients_lock);
|
||||
|
||||
list_for_each_entry_safe(drm, tmp, &host1x->drm_clients, list)
|
||||
if (drm->np == client->dev->of_node)
|
||||
host1x_activate_drm_client(host1x, drm, client);
|
||||
|
||||
if (list_empty(&host1x->drm_clients)) {
|
||||
struct platform_device *pdev = to_platform_device(host1x->dev);
|
||||
|
||||
err = drm_platform_init(&tegra_drm_driver, pdev);
|
||||
if (err < 0) {
|
||||
dev_err(host1x->dev, "drm_platform_init(): %d\n", err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
client->host1x = host1x;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int host1x_unregister_client(struct host1x *host1x,
|
||||
struct host1x_client *client)
|
||||
{
|
||||
struct host1x_drm_client *drm, *tmp;
|
||||
int err;
|
||||
|
||||
list_for_each_entry_safe(drm, tmp, &host1x->drm_active, list) {
|
||||
if (drm->client == client) {
|
||||
err = host1x_drm_exit(host1x);
|
||||
if (err < 0) {
|
||||
dev_err(host1x->dev, "host1x_drm_exit(): %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
host1x_remove_drm_client(host1x, drm);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
mutex_lock(&host1x->clients_lock);
|
||||
list_del_init(&client->list);
|
||||
mutex_unlock(&host1x->clients_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id tegra_host1x_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra30-host1x", },
|
||||
{ .compatible = "nvidia,tegra20-host1x", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_host1x_of_match);
|
||||
|
||||
struct platform_driver tegra_host1x_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-host1x",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra_host1x_of_match,
|
||||
},
|
||||
.probe = tegra_host1x_probe,
|
||||
.remove = tegra_host1x_remove,
|
||||
};
|
||||
|
||||
static int __init tegra_host1x_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = platform_driver_register(&tegra_host1x_driver);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = platform_driver_register(&tegra_dc_driver);
|
||||
if (err < 0)
|
||||
goto unregister_host1x;
|
||||
|
||||
err = platform_driver_register(&tegra_hdmi_driver);
|
||||
if (err < 0)
|
||||
goto unregister_dc;
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_dc:
|
||||
platform_driver_unregister(&tegra_dc_driver);
|
||||
unregister_host1x:
|
||||
platform_driver_unregister(&tegra_host1x_driver);
|
||||
return err;
|
||||
}
|
||||
module_init(tegra_host1x_init);
|
||||
|
||||
static void __exit tegra_host1x_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_hdmi_driver);
|
||||
platform_driver_unregister(&tegra_dc_driver);
|
||||
platform_driver_unregister(&tegra_host1x_driver);
|
||||
}
|
||||
module_exit(tegra_host1x_exit);
|
||||
|
||||
MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -1,272 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/of_i2c.h>
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
static int tegra_connector_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct tegra_output *output = connector_to_output(connector);
|
||||
struct edid *edid = NULL;
|
||||
int err = 0;
|
||||
|
||||
if (output->edid)
|
||||
edid = kmemdup(output->edid, sizeof(*edid), GFP_KERNEL);
|
||||
else if (output->ddc)
|
||||
edid = drm_get_edid(connector, output->ddc);
|
||||
|
||||
drm_mode_connector_update_edid_property(connector, edid);
|
||||
|
||||
if (edid) {
|
||||
err = drm_add_edid_modes(connector, edid);
|
||||
kfree(edid);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tegra_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct tegra_output *output = connector_to_output(connector);
|
||||
enum drm_mode_status status = MODE_OK;
|
||||
int err;
|
||||
|
||||
err = tegra_output_check_mode(output, mode, &status);
|
||||
if (err < 0)
|
||||
return MODE_ERROR;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static struct drm_encoder *
|
||||
tegra_connector_best_encoder(struct drm_connector *connector)
|
||||
{
|
||||
struct tegra_output *output = connector_to_output(connector);
|
||||
|
||||
return &output->encoder;
|
||||
}
|
||||
|
||||
static const struct drm_connector_helper_funcs connector_helper_funcs = {
|
||||
.get_modes = tegra_connector_get_modes,
|
||||
.mode_valid = tegra_connector_mode_valid,
|
||||
.best_encoder = tegra_connector_best_encoder,
|
||||
};
|
||||
|
||||
static enum drm_connector_status
|
||||
tegra_connector_detect(struct drm_connector *connector, bool force)
|
||||
{
|
||||
struct tegra_output *output = connector_to_output(connector);
|
||||
enum drm_connector_status status = connector_status_unknown;
|
||||
|
||||
if (gpio_is_valid(output->hpd_gpio)) {
|
||||
if (gpio_get_value(output->hpd_gpio) == 0)
|
||||
status = connector_status_disconnected;
|
||||
else
|
||||
status = connector_status_connected;
|
||||
} else {
|
||||
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
|
||||
status = connector_status_connected;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void tegra_connector_destroy(struct drm_connector *connector)
|
||||
{
|
||||
drm_sysfs_connector_remove(connector);
|
||||
drm_connector_cleanup(connector);
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs connector_funcs = {
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.detect = tegra_connector_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.destroy = tegra_connector_destroy,
|
||||
};
|
||||
|
||||
static void tegra_encoder_destroy(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_encoder_cleanup(encoder);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_funcs encoder_funcs = {
|
||||
.destroy = tegra_encoder_destroy,
|
||||
};
|
||||
|
||||
static void tegra_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
}
|
||||
|
||||
static bool tegra_encoder_mode_fixup(struct drm_encoder *encoder,
|
||||
const struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static void tegra_encoder_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_encoder_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted)
|
||||
{
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
int err;
|
||||
|
||||
err = tegra_output_enable(output);
|
||||
if (err < 0)
|
||||
dev_err(encoder->dev->dev, "tegra_output_enable(): %d\n", err);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
|
||||
.dpms = tegra_encoder_dpms,
|
||||
.mode_fixup = tegra_encoder_mode_fixup,
|
||||
.prepare = tegra_encoder_prepare,
|
||||
.commit = tegra_encoder_commit,
|
||||
.mode_set = tegra_encoder_mode_set,
|
||||
};
|
||||
|
||||
static irqreturn_t hpd_irq(int irq, void *data)
|
||||
{
|
||||
struct tegra_output *output = data;
|
||||
|
||||
drm_helper_hpd_irq_event(output->connector.dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int tegra_output_parse_dt(struct tegra_output *output)
|
||||
{
|
||||
enum of_gpio_flags flags;
|
||||
struct device_node *ddc;
|
||||
size_t size;
|
||||
int err;
|
||||
|
||||
if (!output->of_node)
|
||||
output->of_node = output->dev->of_node;
|
||||
|
||||
output->edid = of_get_property(output->of_node, "nvidia,edid", &size);
|
||||
|
||||
ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0);
|
||||
if (ddc) {
|
||||
output->ddc = of_find_i2c_adapter_by_node(ddc);
|
||||
if (!output->ddc) {
|
||||
err = -EPROBE_DEFER;
|
||||
of_node_put(ddc);
|
||||
return err;
|
||||
}
|
||||
|
||||
of_node_put(ddc);
|
||||
}
|
||||
|
||||
if (!output->edid && !output->ddc)
|
||||
return -ENODEV;
|
||||
|
||||
output->hpd_gpio = of_get_named_gpio_flags(output->of_node,
|
||||
"nvidia,hpd-gpio", 0,
|
||||
&flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_output_init(struct drm_device *drm, struct tegra_output *output)
|
||||
{
|
||||
int connector, encoder, err;
|
||||
|
||||
if (gpio_is_valid(output->hpd_gpio)) {
|
||||
unsigned long flags;
|
||||
|
||||
err = gpio_request_one(output->hpd_gpio, GPIOF_DIR_IN,
|
||||
"HDMI hotplug detect");
|
||||
if (err < 0) {
|
||||
dev_err(output->dev, "gpio_request_one(): %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = gpio_to_irq(output->hpd_gpio);
|
||||
if (err < 0) {
|
||||
dev_err(output->dev, "gpio_to_irq(): %d\n", err);
|
||||
goto free_hpd;
|
||||
}
|
||||
|
||||
output->hpd_irq = err;
|
||||
|
||||
flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
|
||||
IRQF_ONESHOT;
|
||||
|
||||
err = request_threaded_irq(output->hpd_irq, NULL, hpd_irq,
|
||||
flags, "hpd", output);
|
||||
if (err < 0) {
|
||||
dev_err(output->dev, "failed to request IRQ#%u: %d\n",
|
||||
output->hpd_irq, err);
|
||||
goto free_hpd;
|
||||
}
|
||||
|
||||
output->connector.polled = DRM_CONNECTOR_POLL_HPD;
|
||||
}
|
||||
|
||||
switch (output->type) {
|
||||
case TEGRA_OUTPUT_RGB:
|
||||
connector = DRM_MODE_CONNECTOR_LVDS;
|
||||
encoder = DRM_MODE_ENCODER_LVDS;
|
||||
break;
|
||||
|
||||
case TEGRA_OUTPUT_HDMI:
|
||||
connector = DRM_MODE_CONNECTOR_HDMIA;
|
||||
encoder = DRM_MODE_ENCODER_TMDS;
|
||||
break;
|
||||
|
||||
default:
|
||||
connector = DRM_MODE_CONNECTOR_Unknown;
|
||||
encoder = DRM_MODE_ENCODER_NONE;
|
||||
break;
|
||||
}
|
||||
|
||||
drm_connector_init(drm, &output->connector, &connector_funcs,
|
||||
connector);
|
||||
drm_connector_helper_add(&output->connector, &connector_helper_funcs);
|
||||
|
||||
drm_encoder_init(drm, &output->encoder, &encoder_funcs, encoder);
|
||||
drm_encoder_helper_add(&output->encoder, &encoder_helper_funcs);
|
||||
|
||||
drm_mode_connector_attach_encoder(&output->connector, &output->encoder);
|
||||
drm_sysfs_connector_add(&output->connector);
|
||||
|
||||
output->encoder.possible_crtcs = 0x3;
|
||||
|
||||
return 0;
|
||||
|
||||
free_hpd:
|
||||
gpio_free(output->hpd_gpio);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int tegra_output_exit(struct tegra_output *output)
|
||||
{
|
||||
if (gpio_is_valid(output->hpd_gpio)) {
|
||||
free_irq(output->hpd_irq, output);
|
||||
gpio_free(output->hpd_gpio);
|
||||
}
|
||||
|
||||
if (output->ddc)
|
||||
put_device(&output->ddc->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,228 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Avionic Design GmbH
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "drm.h"
|
||||
#include "dc.h"
|
||||
|
||||
struct tegra_rgb {
|
||||
struct tegra_output output;
|
||||
struct clk *clk_parent;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
|
||||
{
|
||||
return container_of(output, struct tegra_rgb, output);
|
||||
}
|
||||
|
||||
struct reg_entry {
|
||||
unsigned long offset;
|
||||
unsigned long value;
|
||||
};
|
||||
|
||||
static const struct reg_entry rgb_enable[] = {
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
|
||||
};
|
||||
|
||||
static const struct reg_entry rgb_disable[] = {
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
|
||||
{ DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
|
||||
{ DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
|
||||
};
|
||||
|
||||
static void tegra_dc_write_regs(struct tegra_dc *dc,
|
||||
const struct reg_entry *table,
|
||||
unsigned int num)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
tegra_dc_writel(dc, table[i].value, table[i].offset);
|
||||
}
|
||||
|
||||
static int tegra_output_rgb_enable(struct tegra_output *output)
|
||||
{
|
||||
struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
|
||||
|
||||
tegra_dc_write_regs(dc, rgb_enable, ARRAY_SIZE(rgb_enable));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_output_rgb_disable(struct tegra_output *output)
|
||||
{
|
||||
struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
|
||||
|
||||
tegra_dc_write_regs(dc, rgb_disable, ARRAY_SIZE(rgb_disable));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_output_rgb_setup_clock(struct tegra_output *output,
|
||||
struct clk *clk, unsigned long pclk)
|
||||
{
|
||||
struct tegra_rgb *rgb = to_rgb(output);
|
||||
|
||||
return clk_set_parent(clk, rgb->clk_parent);
|
||||
}
|
||||
|
||||
static int tegra_output_rgb_check_mode(struct tegra_output *output,
|
||||
struct drm_display_mode *mode,
|
||||
enum drm_mode_status *status)
|
||||
{
|
||||
/*
|
||||
* FIXME: For now, always assume that the mode is okay. There are
|
||||
* unresolved issues with clk_round_rate(), which doesn't always
|
||||
* reliably report whether a frequency can be set or not.
|
||||
*/
|
||||
|
||||
*status = MODE_OK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_output_ops rgb_ops = {
|
||||
.enable = tegra_output_rgb_enable,
|
||||
.disable = tegra_output_rgb_disable,
|
||||
.setup_clock = tegra_output_rgb_setup_clock,
|
||||
.check_mode = tegra_output_rgb_check_mode,
|
||||
};
|
||||
|
||||
int tegra_dc_rgb_probe(struct tegra_dc *dc)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct tegra_rgb *rgb;
|
||||
int err;
|
||||
|
||||
np = of_get_child_by_name(dc->dev->of_node, "rgb");
|
||||
if (!np || !of_device_is_available(np))
|
||||
return -ENODEV;
|
||||
|
||||
rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
|
||||
if (!rgb)
|
||||
return -ENOMEM;
|
||||
|
||||
rgb->clk = devm_clk_get(dc->dev, NULL);
|
||||
if (IS_ERR(rgb->clk)) {
|
||||
dev_err(dc->dev, "failed to get clock\n");
|
||||
return PTR_ERR(rgb->clk);
|
||||
}
|
||||
|
||||
rgb->clk_parent = devm_clk_get(dc->dev, "parent");
|
||||
if (IS_ERR(rgb->clk_parent)) {
|
||||
dev_err(dc->dev, "failed to get parent clock\n");
|
||||
return PTR_ERR(rgb->clk_parent);
|
||||
}
|
||||
|
||||
err = clk_set_parent(rgb->clk, rgb->clk_parent);
|
||||
if (err < 0) {
|
||||
dev_err(dc->dev, "failed to set parent clock: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
rgb->output.dev = dc->dev;
|
||||
rgb->output.of_node = np;
|
||||
|
||||
err = tegra_output_parse_dt(&rgb->output);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
dc->rgb = &rgb->output;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
|
||||
{
|
||||
struct tegra_rgb *rgb = to_rgb(dc->rgb);
|
||||
int err;
|
||||
|
||||
if (!dc->rgb)
|
||||
return -ENODEV;
|
||||
|
||||
rgb->output.type = TEGRA_OUTPUT_RGB;
|
||||
rgb->output.ops = &rgb_ops;
|
||||
|
||||
err = tegra_output_init(dc->base.dev, &rgb->output);
|
||||
if (err < 0) {
|
||||
dev_err(dc->dev, "output setup failed: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* By default, outputs can be associated with each display controller.
|
||||
* RGB outputs are an exception, so we make sure they can be attached
|
||||
* to only their parent display controller.
|
||||
*/
|
||||
rgb->output.encoder.possible_crtcs = 1 << dc->pipe;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_dc_rgb_exit(struct tegra_dc *dc)
|
||||
{
|
||||
if (dc->rgb) {
|
||||
int err;
|
||||
|
||||
err = tegra_output_disable(dc->rgb);
|
||||
if (err < 0) {
|
||||
dev_err(dc->dev, "output failed to disable: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = tegra_output_exit(dc->rgb);
|
||||
if (err < 0) {
|
||||
dev_err(dc->dev, "output cleanup failed: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
dc->rgb = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
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